Datasheet AD7724 (Analog Devices) - 5

AD7724 (AVDD = 5 V
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5%; DVDD = 5 V
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5%; DVDD1 = 3 V
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5%; AGND = DGND = 0 V, REF2A = TIMING CHARACTERISTICS1, 2 REF2B = 2.5 V, unless otherwise noted.) Limit at TMIN, TMAX Parameter (A Version) Unit Conditions/Comments
fMCLK 100 kHz min Master Clock Frequency 15 MHz max 13 MHz for Specified Performance tDELAY 14 ns max MCLK to SCLK Delay t1 67 ns min Master Clock Period t2 0.45 × tMCLK ns min Master Clock Input High Time t3 0.45 × tMCLK ns min Master Clock Input Low Time t4 15 ns min Data Hold Time After SCLK Rising Edge t5 10 ns min RESET Pulsewidth t6 10 ns min RESET Low Time Before MCLK Rising t7 20 × tMCLK ns max DVAL High Delay After RESET Low t8 3 ns max Data Access Time After SCLK Falling Edge t9 t3–t8 ns max Data Valid Time Before SCLK Rising Edge NOTES 1Sample tested at 25°C to ensure compliance. 2Guaranteed by design.
IOL 1.6mA TO OUTPUT 1.6V PIN CL 50pF IOH 200
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A
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
t1 SCLK (O) t2 t3 t t 9 8 t4 DATA (O) NOTE: O SIGNIFIES AN OUTPUT
Figure 3. Data Timing
MCLK (I) t6 RESET (I) t5 t7 DVAL (O) NOTE: I SIGNIFIES AN INPUT O SIGNIFIES AN OUTPUT
Figure 4. RESET Timing –4– REV. B