Datasheet AD7707 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 3 V/5 V, ±10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC |
| Pages / Page | 53 / 5 — AD7707. SPECIFICATIONS. Table 1. Parameter. B Version. Unit … |
| Revision | B |
| File Format / Size | PDF / 788 Kb |
| Document Language | English |
AD7707. SPECIFICATIONS. Table 1. Parameter. B Version. Unit Conditions/Comments
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AD7707 SPECIFICATIONS
AVDD = DVDD = 3 V or 5 V, REF IN(+) = 1.225 V with AVDD = 3 V and 2.5 V with AVDD = 5 V; REF IN(−) = GND; VBIAS = REFIN(+); MCLK IN = 2.4576 MHz unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted.
Table 1. Parameter B Version 1 Unit Conditions/Comments
STATIC PERFORMANCE Low Level Input Channels (AIN1 and AIN2) No Missing Codes 16 Bits min Guaranteed by design; filter notch < 60 Hz Output Noise See Table 7 to Depends on filter cutoffs and selected gain Table 10 Integral Nonlinearity2 ±0.003 % of FSR max Filter notch < 60 Hz; typically ±0.0003% Unipolar Offset Error3 Unipolar Offset Drift4 0.5 μV/°C typ Bipolar Zero Error3 Bipolar Zero Drift4 0.5 μV/°C typ For gains of 1, 2, and 4 0.1 μV/°C typ For gains of 8, 16, 32, 64, and 128 Positive Full-Scale Error3, 5 Full-Scale Drift4, 6 0.5 μV/°C typ Gain Error3, 7 Gain Drift4, 8 0.5 ppm of FSR/°C typ Bipolar Negative Full-Scale Error2 ±0.003 % of FSR max Typically ±0.0007% Bipolar Negative Full-Scale Drift4 1 μV/°C typ For gains of 1 to 4 0.6 μV/°C typ For gains of 8 to 128 HIGH LEVEL INPUT CHANNEL (AIN3) No Missing Codes 16 Bits min Guaranteed by design; filter notch < 60 Hz Output Noise See Table 11 to Depends on filter cutoffs and selected gain Table 13 Integral Nonlinearity2 ±0.003 % of FSR max Filter notch < 60 Hz; typically ±0.0003% Unipolar Offset Error9 ±10 mV max Typically within ±1.5 mV Unipolar Offset Drift 4 μV/°Ctyp Bipolar Zero Error9 ±10 mV max Typically within ±1.5 mV Bipolar Zero Drift 4 μV/°C typ For gains of 1, 2, and 4 1 μV/°C typ For gains of 8, 16, 32, 64, and 128 Gain Error ±0.2 % typ Typically within ±0.05% Gain Drift 0.5 ppm of FSR/°C typ Negative Full-Scale Error2 ±0.0012 % of FSR typ LOW LEVEL ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN, unless otherwise noted Input Common-Mode Rejection (CMR)2 Low level input channels, AIN1 and AIN2 AVDD = 5 V Gain = 1 100 dB typ Gain = 2 105 dB typ Gain = 4 110 dB typ Gain = 8 to 128 130 dB typ AVDD = 3 V Gain = 1 105 dB typ Gain = 2 110 dB typ Gain = 4 120 dB typ Gain = 8 to 128 130 dB typ Normal-Mode 50 Hz Rejection2 98 dB typ For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × fNOTCH Normal-Mode 60 Hz Rejection2 98 dB typ For filter notches of 10 Hz, 20 Hz, 60 Hz; ±0.02 × fNOTCH Common-Mode 50 Hz Rejection2 150 dB typ For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × fNOTCH Rev. B | Page 4 of 52 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (5 V OPERATION) OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (3 V OPERATION) OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (5 V OPERATION) OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (3 V OPERATION) ON-CHIP REGISTERS COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0) Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 0x01 Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Status: 0x05 Data Register (RS2, RS1, RS0 = 0, 1, 1) Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset Status: 0x00 Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Power-On/Reset Status: 0x1F4000 Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1); Power-On/Reset Status: 0x5761AB CALIBRATION SEQUENCES CIRCUIT DESCRIPTION ANALOG INPUT ANALOG INPUT RANGES INPUT SAMPLE RATE BIPOLAR/UNIPOLAR INPUTS REFERENCE INPUT DIGITAL FILTERING FILTER CHARACTERISTICS POSTFILTERING ANALOG FILTERING CALIBRATION SELF-CALIBRATION SYSTEM CALIBRATION SPAN AND OFFSET LIMITS ON THE LOW LEVEL INPUT CHANNELS, AIN1 AND AIN2 SPAN AND OFFSET LIMITS ON THE HIGH LEVEL INPUT CHANNEL AIN3 POWER-UP AND CALIBRATION USING THE AD7707 CLOCKING AND OSCILLATOR CIRCUIT SYSTEM SYNCHRONIZATION RESET INPUT STANDBY MODE ACCURACY DRIFT CONSIDERATIONS POWER SUPPLIES SUPPLY CURRENT GROUNDING AND LAYOUT DIGITAL INTERFACE CONFIGURING THE AD7707 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7707 TO 68HC11 INTERFACE AD7707 TO 8XC51 INTERFACE CODE FOR SETTING UP THE AD7707 C CODE FOR INTERFACING AD7707 TO 68HC11 APPLICATIONS INFORMATION DATA ACQUISITION SMART VALVE/ACTUATOR CONTROL PRESSURE MEASUREMENT THERMOCOUPLE MEASUREMENT RTD MEASUREMENT CHART RECORDERS ACCOMMODATING VARIOUS HIGH LEVEL INPUT RANGES TYPICAL INPUT CURRENTS OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL, AIN3 5 V OPERATION 3 V OPERATION OUTLINE DIMENSIONS ORDERING GUIDE
AD7707 SPECIFICATIONS
AVDD = DVDD = 3 V or 5 V, REF IN(+) = 1.225 V with AVDD = 3 V and 2.5 V with AVDD = 5 V; REF IN(−) = GND; VBIAS = REFIN(+); MCLK IN = 2.4576 MHz unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted.
Table 1. Parameter B Version 1 Unit Conditions/Comments
STATIC PERFORMANCE Low Level Input Channels (AIN1 and AIN2) No Missing Codes 16 Bits min Guaranteed by design; filter notch < 60 Hz Output Noise See Table 7 to Depends on filter cutoffs and selected gain Table 10 Integral Nonlinearity2 ±0.003 % of FSR max Filter notch < 60 Hz; typically ±0.0003% Unipolar Offset Error3 Unipolar Offset Drift4 0.5 μV/°C typ Bipolar Zero Error3 Bipolar Zero Drift4 0.5 μV/°C typ For gains of 1, 2, and 4 0.1 μV/°C typ For gains of 8, 16, 32, 64, and 128 Positive Full-Scale Error3, 5 Full-Scale Drift4, 6 0.5 μV/°C typ Gain Error3, 7 Gain Drift4, 8 0.5 ppm of FSR/°C typ Bipolar Negative Full-Scale Error2 ±0.003 % of FSR max Typically ±0.0007% Bipolar Negative Full-Scale Drift4 1 μV/°C typ For gains of 1 to 4 0.6 μV/°C typ For gains of 8 to 128 HIGH LEVEL INPUT CHANNEL (AIN3) No Missing Codes 16 Bits min Guaranteed by design; filter notch < 60 Hz Output Noise See Table 11 to Depends on filter cutoffs and selected gain Table 13 Integral Nonlinearity2 ±0.003 % of FSR max Filter notch < 60 Hz; typically ±0.0003% Unipolar Offset Error9 ±10 mV max Typically within ±1.5 mV Unipolar Offset Drift 4 μV/°Ctyp Bipolar Zero Error9 ±10 mV max Typically within ±1.5 mV Bipolar Zero Drift 4 μV/°C typ For gains of 1, 2, and 4 1 μV/°C typ For gains of 8, 16, 32, 64, and 128 Gain Error ±0.2 % typ Typically within ±0.05% Gain Drift 0.5 ppm of FSR/°C typ Negative Full-Scale Error2 ±0.0012 % of FSR typ LOW LEVEL ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN, unless otherwise noted Input Common-Mode Rejection (CMR)2 Low level input channels, AIN1 and AIN2 AVDD = 5 V Gain = 1 100 dB typ Gain = 2 105 dB typ Gain = 4 110 dB typ Gain = 8 to 128 130 dB typ AVDD = 3 V Gain = 1 105 dB typ Gain = 2 110 dB typ Gain = 4 120 dB typ Gain = 8 to 128 130 dB typ Normal-Mode 50 Hz Rejection2 98 dB typ For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × fNOTCH Normal-Mode 60 Hz Rejection2 98 dB typ For filter notches of 10 Hz, 20 Hz, 60 Hz; ±0.02 × fNOTCH Common-Mode 50 Hz Rejection2 150 dB typ For filter notches of 10 Hz, 25 Hz, 50 Hz; ±0.02 × fNOTCH Rev. B | Page 4 of 52 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (5 V OPERATION) OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (3 V OPERATION) OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (5 V OPERATION) OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (3 V OPERATION) ON-CHIP REGISTERS COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0) Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 0x01 Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Status: 0x05 Data Register (RS2, RS1, RS0 = 0, 1, 1) Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset Status: 0x00 Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Power-On/Reset Status: 0x1F4000 Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1); Power-On/Reset Status: 0x5761AB CALIBRATION SEQUENCES CIRCUIT DESCRIPTION ANALOG INPUT ANALOG INPUT RANGES INPUT SAMPLE RATE BIPOLAR/UNIPOLAR INPUTS REFERENCE INPUT DIGITAL FILTERING FILTER CHARACTERISTICS POSTFILTERING ANALOG FILTERING CALIBRATION SELF-CALIBRATION SYSTEM CALIBRATION SPAN AND OFFSET LIMITS ON THE LOW LEVEL INPUT CHANNELS, AIN1 AND AIN2 SPAN AND OFFSET LIMITS ON THE HIGH LEVEL INPUT CHANNEL AIN3 POWER-UP AND CALIBRATION USING THE AD7707 CLOCKING AND OSCILLATOR CIRCUIT SYSTEM SYNCHRONIZATION RESET INPUT STANDBY MODE ACCURACY DRIFT CONSIDERATIONS POWER SUPPLIES SUPPLY CURRENT GROUNDING AND LAYOUT DIGITAL INTERFACE CONFIGURING THE AD7707 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7707 TO 68HC11 INTERFACE AD7707 TO 8XC51 INTERFACE CODE FOR SETTING UP THE AD7707 C CODE FOR INTERFACING AD7707 TO 68HC11 APPLICATIONS INFORMATION DATA ACQUISITION SMART VALVE/ACTUATOR CONTROL PRESSURE MEASUREMENT THERMOCOUPLE MEASUREMENT RTD MEASUREMENT CHART RECORDERS ACCOMMODATING VARIOUS HIGH LEVEL INPUT RANGES TYPICAL INPUT CURRENTS OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL, AIN3 5 V OPERATION 3 V OPERATION OUTLINE DIMENSIONS ORDERING GUIDE
