Datasheet AD7707 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 3 V/5 V, ±10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC |
| Pages / Page | 53 / 7 — AD7707. Parameter. B Version1 Unit. Conditions/Comments |
| Revision | B |
| File Format / Size | PDF / 788 Kb |
| Document Language | English |
AD7707. Parameter. B Version1 Unit. Conditions/Comments
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AD7707 Parameter B Version1 Unit Conditions/Comments
MCLK IN Only DVDD = 5 V nominal VINL, Input Low Voltage 0.8 V max VINH, Input High Voltage 3.5 V min MCLK IN Only DVDD = 3 V nominal VINL, Input Low Voltage 0.4 V max VINH, Input High Voltage 2.5 V min LOGIC OUTPUTS (Including MCLK OUT) VOL, Output Low Voltage 0.4 V max ISINK = 800 μA except for MCLK OUT13; DVDD = 5 V 0.4 V max ISINK = 100 μA except for MCLK OUT13; DVDD = 3 V VOH, Output High Voltage 4 V min ISOURCE = 200 μA except for MCLK OUT13; DVDD = 5 V DVDD − 0.6 V min ISOURCE = 100 μA except for MCLK OUT13; DVDD = 3 V Floating State Leakage Current ±10 μA max Floating State Output Capacitance14 9 pF typ Data Output Coding Binary Unipolar mode Offset binary Bipolar mode SYSTEM CALIBRATION Low Level Input Channels (AIN1 and AIN2) Positive Full-Scale Calibration Limit15 (1.05 × V max Gain is the selected PGA gain (1 to 128) VREF)/gain Negative Full-Scale Calibration Limit15 −(1.05 × V max Gain is the selected PGA gain (1 to 128) VREF)/gain Offset Calibration Limit16 −(1.05 × V max Gain is the selected PGA gain (1 to 128) VREF)/gain Input Span16 (0.8 × VREF)/gain V min Gain is the selected PGA gain (1 to 128) (2.1 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) High Level Input Channels (AIN3) Positive Full-Scale Calibration Limit15 (8.4 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) Negative Full-Scale Calibration Limit15 −(8.4 × V max Gain is the selected PGA gain (1 to 128) VREF)/gain Offset Calibration Limit16 −(8.4 × V max Gain is the selected PGA gain (1 to 128) VREF)/gain Input Span16 (6.4 × VREF)/gain V min Gain is the selected PGA gain (1 to 128) (16.8 × V max Gain is the selected PGA gain (1 to 128) VREF)/gain POWER REQUIREMENTS Power Supply Voltages AVDD Voltage 2.7 to 3.3 or 4.75 to 5.25 V min to V max For specified performance DVDD Voltage 2.7 to 5.25 V min to V max For specified performance Power Supply Currents AVDD Current AVDD = 3 V or 5 V; gain = 1 to 4 0.27 mA max Typically 0.22 mA; BUF = 0; fCLK IN = 1 MHz or 2.4576 MHz 0.6 mA max Typically 0.45 mA; BUF = 1; fCLK IN = 1 MHz or 2.4576 MHz AVDD = 3 V or 5 V; gain = 8 to 128 0.5 mA max Typically 0.38 mA; BUF = 0; fCLK IN = 2.4576 MHz 1.1 mA max Typically 0.81 mA; BUF = 1; fCLK IN = 2.4576 MHz POWER REQUIREMENTS (Continued) DVDD Current17 Digital inputs = 0 V or DVDD; external MCLK IN 0.080 mA max Typically 0.06 mA; DVDD = 3 V; fCLK IN = 1 MHz 0.15 mA max Typically 0.13 mA; DVDD = 5 V; fCLK IN = 1 MHz 0.18 mA max Typically 0.15 mA; DVDD = 3 V; fCLK IN = 2.4576 MHz 0.35 mA max Typically 0.3 mA; DVDD = 5 V; fCLK IN = 2.4576 MHz Power Supply Rejection18, 19 dB typ Rev. B | Page 6 of 52 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (5 V OPERATION) OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (3 V OPERATION) OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (5 V OPERATION) OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (3 V OPERATION) ON-CHIP REGISTERS COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0) Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 0x01 Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Status: 0x05 Data Register (RS2, RS1, RS0 = 0, 1, 1) Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset Status: 0x00 Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Power-On/Reset Status: 0x1F4000 Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1); Power-On/Reset Status: 0x5761AB CALIBRATION SEQUENCES CIRCUIT DESCRIPTION ANALOG INPUT ANALOG INPUT RANGES INPUT SAMPLE RATE BIPOLAR/UNIPOLAR INPUTS REFERENCE INPUT DIGITAL FILTERING FILTER CHARACTERISTICS POSTFILTERING ANALOG FILTERING CALIBRATION SELF-CALIBRATION SYSTEM CALIBRATION SPAN AND OFFSET LIMITS ON THE LOW LEVEL INPUT CHANNELS, AIN1 AND AIN2 SPAN AND OFFSET LIMITS ON THE HIGH LEVEL INPUT CHANNEL AIN3 POWER-UP AND CALIBRATION USING THE AD7707 CLOCKING AND OSCILLATOR CIRCUIT SYSTEM SYNCHRONIZATION RESET INPUT STANDBY MODE ACCURACY DRIFT CONSIDERATIONS POWER SUPPLIES SUPPLY CURRENT GROUNDING AND LAYOUT DIGITAL INTERFACE CONFIGURING THE AD7707 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7707 TO 68HC11 INTERFACE AD7707 TO 8XC51 INTERFACE CODE FOR SETTING UP THE AD7707 C CODE FOR INTERFACING AD7707 TO 68HC11 APPLICATIONS INFORMATION DATA ACQUISITION SMART VALVE/ACTUATOR CONTROL PRESSURE MEASUREMENT THERMOCOUPLE MEASUREMENT RTD MEASUREMENT CHART RECORDERS ACCOMMODATING VARIOUS HIGH LEVEL INPUT RANGES TYPICAL INPUT CURRENTS OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL, AIN3 5 V OPERATION 3 V OPERATION OUTLINE DIMENSIONS ORDERING GUIDE
AD7707 Parameter B Version1 Unit Conditions/Comments
MCLK IN Only DVDD = 5 V nominal VINL, Input Low Voltage 0.8 V max VINH, Input High Voltage 3.5 V min MCLK IN Only DVDD = 3 V nominal VINL, Input Low Voltage 0.4 V max VINH, Input High Voltage 2.5 V min LOGIC OUTPUTS (Including MCLK OUT) VOL, Output Low Voltage 0.4 V max ISINK = 800 μA except for MCLK OUT13; DVDD = 5 V 0.4 V max ISINK = 100 μA except for MCLK OUT13; DVDD = 3 V VOH, Output High Voltage 4 V min ISOURCE = 200 μA except for MCLK OUT13; DVDD = 5 V DVDD − 0.6 V min ISOURCE = 100 μA except for MCLK OUT13; DVDD = 3 V Floating State Leakage Current ±10 μA max Floating State Output Capacitance14 9 pF typ Data Output Coding Binary Unipolar mode Offset binary Bipolar mode SYSTEM CALIBRATION Low Level Input Channels (AIN1 and AIN2) Positive Full-Scale Calibration Limit15 (1.05 × V max Gain is the selected PGA gain (1 to 128) VREF)/gain Negative Full-Scale Calibration Limit15 −(1.05 × V max Gain is the selected PGA gain (1 to 128) VREF)/gain Offset Calibration Limit16 −(1.05 × V max Gain is the selected PGA gain (1 to 128) VREF)/gain Input Span16 (0.8 × VREF)/gain V min Gain is the selected PGA gain (1 to 128) (2.1 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) High Level Input Channels (AIN3) Positive Full-Scale Calibration Limit15 (8.4 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) Negative Full-Scale Calibration Limit15 −(8.4 × V max Gain is the selected PGA gain (1 to 128) VREF)/gain Offset Calibration Limit16 −(8.4 × V max Gain is the selected PGA gain (1 to 128) VREF)/gain Input Span16 (6.4 × VREF)/gain V min Gain is the selected PGA gain (1 to 128) (16.8 × V max Gain is the selected PGA gain (1 to 128) VREF)/gain POWER REQUIREMENTS Power Supply Voltages AVDD Voltage 2.7 to 3.3 or 4.75 to 5.25 V min to V max For specified performance DVDD Voltage 2.7 to 5.25 V min to V max For specified performance Power Supply Currents AVDD Current AVDD = 3 V or 5 V; gain = 1 to 4 0.27 mA max Typically 0.22 mA; BUF = 0; fCLK IN = 1 MHz or 2.4576 MHz 0.6 mA max Typically 0.45 mA; BUF = 1; fCLK IN = 1 MHz or 2.4576 MHz AVDD = 3 V or 5 V; gain = 8 to 128 0.5 mA max Typically 0.38 mA; BUF = 0; fCLK IN = 2.4576 MHz 1.1 mA max Typically 0.81 mA; BUF = 1; fCLK IN = 2.4576 MHz POWER REQUIREMENTS (Continued) DVDD Current17 Digital inputs = 0 V or DVDD; external MCLK IN 0.080 mA max Typically 0.06 mA; DVDD = 3 V; fCLK IN = 1 MHz 0.15 mA max Typically 0.13 mA; DVDD = 5 V; fCLK IN = 1 MHz 0.18 mA max Typically 0.15 mA; DVDD = 3 V; fCLK IN = 2.4576 MHz 0.35 mA max Typically 0.3 mA; DVDD = 5 V; fCLK IN = 2.4576 MHz Power Supply Rejection18, 19 dB typ Rev. B | Page 6 of 52 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (5 V OPERATION) OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (3 V OPERATION) OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (5 V OPERATION) OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (3 V OPERATION) ON-CHIP REGISTERS COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0) Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 0x01 Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Status: 0x05 Data Register (RS2, RS1, RS0 = 0, 1, 1) Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset Status: 0x00 Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Power-On/Reset Status: 0x1F4000 Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1); Power-On/Reset Status: 0x5761AB CALIBRATION SEQUENCES CIRCUIT DESCRIPTION ANALOG INPUT ANALOG INPUT RANGES INPUT SAMPLE RATE BIPOLAR/UNIPOLAR INPUTS REFERENCE INPUT DIGITAL FILTERING FILTER CHARACTERISTICS POSTFILTERING ANALOG FILTERING CALIBRATION SELF-CALIBRATION SYSTEM CALIBRATION SPAN AND OFFSET LIMITS ON THE LOW LEVEL INPUT CHANNELS, AIN1 AND AIN2 SPAN AND OFFSET LIMITS ON THE HIGH LEVEL INPUT CHANNEL AIN3 POWER-UP AND CALIBRATION USING THE AD7707 CLOCKING AND OSCILLATOR CIRCUIT SYSTEM SYNCHRONIZATION RESET INPUT STANDBY MODE ACCURACY DRIFT CONSIDERATIONS POWER SUPPLIES SUPPLY CURRENT GROUNDING AND LAYOUT DIGITAL INTERFACE CONFIGURING THE AD7707 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7707 TO 68HC11 INTERFACE AD7707 TO 8XC51 INTERFACE CODE FOR SETTING UP THE AD7707 C CODE FOR INTERFACING AD7707 TO 68HC11 APPLICATIONS INFORMATION DATA ACQUISITION SMART VALVE/ACTUATOR CONTROL PRESSURE MEASUREMENT THERMOCOUPLE MEASUREMENT RTD MEASUREMENT CHART RECORDERS ACCOMMODATING VARIOUS HIGH LEVEL INPUT RANGES TYPICAL INPUT CURRENTS OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL, AIN3 5 V OPERATION 3 V OPERATION OUTLINE DIMENSIONS ORDERING GUIDE
