Datasheet AD7470, AD7472 (Analog Devices)

a
1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs AD7470/AD7472 FUNCTIONAL BLOCK DIAGRAM FEATURES Specified for VDD of 2.7 V to 5.25 V AVDD DVDD REF IN VDRIVE 1.75 MSPS for AD7470 (10-Bit) 1.5 MSPS for AD7472 (12-Bit) Low Power 10-/12-BIT DB9 (DB11) AD7470: 3.34 mW Typ at 1.5 MSPS with 3 V Supplies SUCCESSIVE OUTPUT V T/H IN APPROXIMATION 7.97 mW Typ at 1.75 MSPS with 5 V Supplies DRIVERS ADC DB0 AD7472: 3.54 mW Typ at 1.2 MSPS with 3 V Supplies 8.7 mW Typ at 1.5 MSPS with 5 V Supplies Wide Input Bandwidth CLK IN 70 dB Typ SNR at 500 kHz Input Frequency Flexible Power/Throughput Rate Management CONVST CONTROL CS LOGIC No Pipeline Delays RD High Speed Parallel Interface BUSY Sleep Mode: 50 nA Typ AD7470/AD7472 24-Lead SOIC and TSSOP Packages AGND DGND GENERAL DESCRIPTION AD7470 IS A 10-BIT PART WITH DB0 TO DB9 AS OUTPUTS.
The AD7470/AD7472 are 10-bit/12-bit high speed, low power,
AD7472 IS A 12-BIT PART WITH DB0 TO DB11 AS OUTPUTS.
successive approximation ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1.5 MSPS for the 12-bit AD7472 and up to 1.75 MSPS for the It is also possible to operate the parts in an auto sleep mode, 10-bit AD7470. The parts contain a low noise, wide bandwidth where the part wakes up to do a conversion and automatically track-and-hold amplifier that can handle input frequencies in enters sleep mode at the end of conversion. This method allows excess of 1 MHz. very low power dissipation numbers at lower throughput rates. In this mode, the AD7472 can be operated with 3 V supplies at The conversion process and data acquisition are controlled 100 kSPS, and consume an average current of just 124 µA. At using standard control inputs, allowing easy interfacing to 5 V supplies and 100 kSPS, the average current consumption is microprocessors or DSPs. The input signal is sampled on the 171 µA. falling edge of CONVST, and conversion is also initiated at this point. BUSY goes high at the start of conversion and The analog input range for the part is 0 V to REF IN. The 2.5 V goes low 531.66 ns after falling edge of CONVST (AD7472 reference is applied externally to the REF IN pin. The conver- with a clock frequency of 26 MHz) to indicate that the con- sion rate is determined by the externally-applied clock. version is complete. There are no pipeline delays associated with the parts. The conversion result is accessed via standard
PRODUCT HIGHLIGHTS
CS and RD signals over a high speed parallel interface. 1. High Throughput with Low Power Consumption. The AD7470 offers 1.75 MSPS throughput and the AD7472 The AD7470/AD7472 use advanced design techniques to offers 1.5 MSPS throughput rates with 4 mW power achieve very low power dissipation at high throughput rates. With consumption. 3 V supplies and 1.5 MSPS throughput rates, the AD7470 typically consumes, on average, just 1.1 mA. With 5 V supplies 2. Flexible Power/Throughput Rate Management. The conver- and 1.75 MSPS, the average current consumption is typically sion rate is determined by an externally-applied clock allow- 1.6 mA. The part also offers flexible power/throughput rate ing the power to be reduced as the conversion rate is reduced. management. Operating the AD7470 with 3 V supplies and The part also features an auto sleep mode to maximize power 500 kSPS throughput reduces the current consumption to 713 µA. efficiency at lower throughput rates. At 5 V supplies and 500 kSPS, the part consumes 944 µA. 3. No Pipeline Delay. The part features a standard successive approximation ADC with accurate control of the sampling instant via a CONVST input and once off conversion control. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
under any patent or patent rights of Analog Devices. Trademarks and
Tel: 781/329-4700 www.analog.com
registered trademarks are the property of their respective owners.
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Track-and-Hold Acquisition Time Signal to (Noise + Distortion) Ratio Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion Aperture Delay Aperture Jitter CIRCUIT DESCRIPTION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM ADC TRANSFER FUNCTION AC ACQUISITION TIME Reference Input DC ACQUISITION TIME ANALOG INPUT CLOCK SOURCES PARALLEL INTERFACE OPERATING MODES Mode 1 (High Speed Sampling) Mode 2 (Sleep Mode) Burst Mode VDRIVE POWER-UP Power vs. Throughput Mode 1 Mode 2 Typical Performance Characteristics GROUNDING AND LAYOUT POWER SUPPLIES MICROPROCESSOR INTERFACING AD7470/AD7472 to ADSP-2185 Interface AD7470/AD7472 to ADSP-21065 Interface AD7470/AD7472 to TMS320C25 Interface AD7470/AD7472 to PIC17C4x Interface AD7470/AD7472 to 80C186 Interface OUTLINE DIMENSIONS Revision History