Datasheet AD9201 (Analog Devices) - 6

ManufacturerAnalog Devices
DescriptionDual Channel 20 MHz 10-Bit Resolution CMOS ADC
Pages / Page21 / 6 — AD9201. AVDD. DRVDD. DRVSS. AVSS. REFBS. REFBF. OFFSET ERROR. GAIN MATCH. …
RevisionD
File Format / SizePDF / 473 Kb
Document LanguageEnglish

AD9201. AVDD. DRVDD. DRVSS. AVSS. REFBS. REFBF. OFFSET ERROR. GAIN MATCH. OFFSET MATCH. PIPELINE DELAY (LATENCY)

AD9201 AVDD DRVDD DRVSS AVSS REFBS REFBF OFFSET ERROR GAIN MATCH OFFSET MATCH PIPELINE DELAY (LATENCY)

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AD9201 AVDD DRVDD AVDD AVDD AVDD AVDD DRVSS AVSS AVSS DRVSS AVSS AVSS AVSS
a. D0–D9, OTR b. Three-State, Standby c. CLK
AVDD AVDD AVDD AVDD AVDD IN REFBS AVSS AVDD AVSS REFBF AVSS AVSS AVSS AVSS
d. INA, INB e. Reference f. REFSENSE g. VREF Figure 2. Equivalent Circuits
OFFSET ERROR
scale. Gain error is the deviation of the actual difference be- The first transition should occur at a level 1 LSB above “zero.” tween first and last code transitions and the ideal difference Offset is defined as the deviation of the actual first code transi- between the first and last code transitions. tion from that point.
GAIN MATCH OFFSET MATCH
The change in gain error between I and Q channels. The change in offset error between I and Q channels.
PIPELINE DELAY (LATENCY) EFFECTIVE NUMBER OF BITS (ENOB)
The number of clock cycles between conversion initiation and For a sine wave, SINAD can be expressed in terms of the num- the associated output data being made available. New output ber of bits. Using the following formula, data is provided every rising clock edge. N = (SINAD – 1.76)/6.02
MUX SELECT DELAY
It is possible to get a measure of performance expressed as N, The delay between the change in SELECT pin data level and the effective number of bits. valid data on output pins. Thus, effective number of bits for a device for sine wave inputs
POWER SUPPLY REJECTION
at a given input frequency can be calculated directly from its The specification shows the maximum change in full scale from measured SINAD. the value with the supply at the minimum limit to the value with the supply at its maximum limit.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
APERTURE JITTER
ponents to the rms value of the measured input signal and Aperture jitter is the variation in aperture delay for successive is expressed as a percentage or in decibels. samples and is manifested as noise on the input to the A/D.
SIGNAL-TO-NOISE RATIO (SNR) APERTURE DELAY
SNR is the ratio of the rms value of the measured input signal to Aperture delay is a measure of the Sample-and-Hold Amplifier the rms sum of all other spectral components below the Nyquist (SHA) performance and is measured from the rising edge of the frequency, excluding the first six harmonics and dc. The value clock input to when the input signal is held for conversion. for SNR is expressed in decibels.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) SPURIOUS FREE DYNAMIC RANGE (SFDR) RATIO
The difference in dB between the rms amplitude of the input S/N+D is the ratio of the rms value of the measured input signal signal and the peak spurious signal. to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc.
GAIN ERROR
The value for S/N+D is expressed in decibels. The first code transition should occur for an analog value 1 LSB above nominal negative full scale. The last transition should occur for an analog value 1 LSB below the nominal positive full REV. D –5–