Datasheet AD7864 (Analog Devices) - 9

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AD7864 Pin No. Mnemonic Description
27 INT/EXT CLK Internal/External Clock Select Input. When this pin is at Logic 0, the AD7864 uses its internally generated master clock. When this pin is at Logic 1, the master clock is generated externally to the device. 28 CLKIN Conversion Clock Input. This is an externally applied clock that allows the user to control the conversion rate of the AD7864. Each conversion needs 14 clock cycles for the conversion to be completed and an EOC pulse to be generated. The clock should have a duty cycle that is no worse than 60/40. See the Using An Exte rnal Clock section. 29 to 34 DB11 to DB6 Data Bit 11 is the MSB, followed by Data Bit 10 to Data Bit 6. Three-state TTL outputs. Output coding is twos complement for the AD7864-1 and AD7864-3. Output coding is straight (natural) binary for the AD7864-2. 35 DVDD Positive Supply Voltage for Digital Section, 5.0 V ± 5%. Connect a 0.1 μF decoupling capacitor between this pin and AGND. Both DVDD and AVDD should be externally tied together. 36 VDRIVE This pin provides the positive supply voltage for the output drivers (DB0 to DB11), BUSY, EOC, and FRSTDATA. It is normally tied to DVDD. Decouple VDRIVE with a 0.1 μF capacitor to improve performance when reading during the conversion sequence. To facilitate interfacing to 3 V processors and DSPs, the output data drivers can also be powered by a 3 V ± 10% supply. 37 DGND Digital Ground. This is the ground reference for digital circuitry. Connect this DGND pin to the AGND plane of the system at the AGND pin. 38, 39 DB5, DB4 Data Bit 5 to Data Bit 4. Three-state TTL outputs. 40 to 43 DB3 to DB0 Data Bit 3 to Data Bit 0. Bidirectional data pins. When a read operation takes place, these pins are three-state TTL outputs. The channel select register is programmed with the data on the DB0 to DB3 pins with standard CS and WR signals. DB0 represents Channel 1, and DB3 represents Channel 4. 44 EOC End-of-Conversion. Active low logic output indicating conversion status. The end of each conversion in a conversion sequence is indicated by a low-going pulse on this line. Rev. D | Page 8 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY THEORY OF OPERATION CONVERTER DETAILS Track-and-Hold Amplifiers Reference CIRCUIT DESCRIPTION ANALOG INPUT AD7864-1 AD7864-2 AD7864-3 SELECTING A CONVERSION SEQUENCE TIMING AND CONTROL Reading Between Each Conversion in the Conversion Sequence Reading After the Conversion Sequence USING AN EXTERNAL CLOCK STANDBY MODE OPERATION ACCESSING THE OUTPUT DATA REGISTERS OFFSET AND FULL-SCALE ADJUSTMENT POSITIVE FULL-SCALE ADJUST NEGATIVE FULL-SCALE ADJUST DYNAMIC SPECIFICATIONS SIGNAL-TO-NOISE RATIO (SNR) EFFECTIVE NUMBER OF BITS INTERMODULATION DISTORTION AC LINEARITY PLOTS MEASURING APERTURE JITTER MICROPROCESSOR INTERFACING AD7864 TO ADSP-2100/ADSP-2101/ADSP-2102 INTERFACE AD7864 TO TMS320C5x INTERFACE AD7864 TO MC68HC000 INTERFACE VECTOR MOTOR CONTROL MULTIPLE AD7864S IN A SYSTEM OUTLINE DIMENSIONS ORDERING GUIDE