Datasheet AD6640 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Multi-Channel, Multi-Mode Receiver Chipset |
| Pages / Page | 25 / 7 — AD6640. DEFINITION OF SPECIFICATIONS. Power Supply Rejection Ratio. … |
| Revision | A |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
AD6640. DEFINITION OF SPECIFICATIONS. Power Supply Rejection Ratio. Analog Bandwidth (Small Signal)
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AD6640 DEFINITION OF SPECIFICATIONS Power Supply Rejection Ratio Analog Bandwidth (Small Signal)
The ratio of a change in input offset voltage to a change in The analog input frequency at which the spectral power of the power supply voltage. fundamental frequency (as determined by the FFT analysis) is
Signal-to-Noise-and-Distortion (SINAD)
reduced by 3 dB. The ratio of the rms signal amplitude (set at 1 dB below full
Aperture Delay
scale) to the rms value of the sum of all other spectral compo- The delay between a differential crossing of ENCODE and nents, including harmonics but excluding dc. ENCODE and the instant at which the analog input is sampled.
Signal-to-Noise Ratio (SNR) Aperture Uncertainty (Jitter)
The ratio of the rms signal amplitude (set at 1 dB below full scale) The sample-to-sample variation in aperture delay. to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the peak
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the ENCODE spurious spectral component. The peak spurious component may pulse should be left in Logic “1” state to achieve rated performance; or may not be a harmonic. May be reported in dBc (i.e., degrades pulsewidth low is the minimum time ENCODE pulse should be as signal levels is lowered), or in dBFS (always related back to left in low state. At a given clock rate, these specifications define converter full scale). an acceptable ENCODE duty cycle.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
Integral Nonlinearity
The deviation of the transfer function from a reference line mea- of the worst third order intermodulation product; reported in dBc. sured in fractions of 1 LSB using a “best straight line” determined
Two-Tone SFDR
by a least square curve fit. The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component
Minimum Conversion Rate
The ENCODE rate at which the SNR of the lowest analog signal may or may not be an IMD product. May be reported in dBc frequency drops by no more than 3 dB below the guaranteed limit. (i.e., degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).
Maximum Conversion Rate
The ENCODE rate at which parametric testing is performed.
Worst Harmonic
The ratio of the rms signal amplitude to the rms value of the
Output Propagation Delay
worst harmonic component, reported in dBc. The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. –6– REV. A Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS AC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION DEFINITION OF SPECIFICATIONS Analog Bandwidth (Small Signal) Aperture Delay Aperture Uncertainty (Jitter) Differential Nonlinearity Encode Pulsewidth/Duty Cycle Integral Nonlinearity Minimum Conversion Rate Maximum Conversion Rate Output Propagation Delay Power Supply Rejection Ratio Signal-to-Noise-and-Distortion (SINAD) Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR Worst Harmonic Equivalent Circuits Typical Performance Characteristics THEORY OF OPERATION APPLYING THE AD6640 Encoding the AD6640 Driving the Analog Input Power Supplies Output Loading Layout Information Evaluation Boards DIGITAL WIDEBAND RECEIVERS Introduction System Description System Requirements Noise Floor and SNR Processing Gain Overcoming Static Nonlinearities with Dither Receiver Example IF Sampling Using the AD6640 as a Mix-Down Stage RECEIVE CHAIN FOR A PHASED-ARRAY CELLULAR BASE STATION OUTLINE DIMENSIONS Revision History
The ratio of a change in input offset voltage to a change in The analog input frequency at which the spectral power of the power supply voltage. fundamental frequency (as determined by the FFT analysis) is
Signal-to-Noise-and-Distortion (SINAD)
reduced by 3 dB. The ratio of the rms signal amplitude (set at 1 dB below full
Aperture Delay
scale) to the rms value of the sum of all other spectral compo- The delay between a differential crossing of ENCODE and nents, including harmonics but excluding dc. ENCODE and the instant at which the analog input is sampled.
Signal-to-Noise Ratio (SNR) Aperture Uncertainty (Jitter)
The ratio of the rms signal amplitude (set at 1 dB below full scale) The sample-to-sample variation in aperture delay. to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the peak
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the ENCODE spurious spectral component. The peak spurious component may pulse should be left in Logic “1” state to achieve rated performance; or may not be a harmonic. May be reported in dBc (i.e., degrades pulsewidth low is the minimum time ENCODE pulse should be as signal levels is lowered), or in dBFS (always related back to left in low state. At a given clock rate, these specifications define converter full scale). an acceptable ENCODE duty cycle.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
Integral Nonlinearity
The deviation of the transfer function from a reference line mea- of the worst third order intermodulation product; reported in dBc. sured in fractions of 1 LSB using a “best straight line” determined
Two-Tone SFDR
by a least square curve fit. The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component
Minimum Conversion Rate
The ENCODE rate at which the SNR of the lowest analog signal may or may not be an IMD product. May be reported in dBc frequency drops by no more than 3 dB below the guaranteed limit. (i.e., degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).
Maximum Conversion Rate
The ENCODE rate at which parametric testing is performed.
Worst Harmonic
The ratio of the rms signal amplitude to the rms value of the
Output Propagation Delay
worst harmonic component, reported in dBc. The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. –6– REV. A Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS AC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION DEFINITION OF SPECIFICATIONS Analog Bandwidth (Small Signal) Aperture Delay Aperture Uncertainty (Jitter) Differential Nonlinearity Encode Pulsewidth/Duty Cycle Integral Nonlinearity Minimum Conversion Rate Maximum Conversion Rate Output Propagation Delay Power Supply Rejection Ratio Signal-to-Noise-and-Distortion (SINAD) Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR Worst Harmonic Equivalent Circuits Typical Performance Characteristics THEORY OF OPERATION APPLYING THE AD6640 Encoding the AD6640 Driving the Analog Input Power Supplies Output Loading Layout Information Evaluation Boards DIGITAL WIDEBAND RECEIVERS Introduction System Description System Requirements Noise Floor and SNR Processing Gain Overcoming Static Nonlinearities with Dither Receiver Example IF Sampling Using the AD6640 as a Mix-Down Stage RECEIVE CHAIN FOR A PHASED-ARRAY CELLULAR BASE STATION OUTLINE DIMENSIONS Revision History
