Datasheet AD7720 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | CMOS Sigma-Delta Modulator with 90 dB Dynamic Range |
| Pages / Page | 17 / 5 — AD7720 TIMING CHARACTERISTICS (AVDD = +5 V. 5%; DVDD = +5 V. 5%; AGND = … |
| File Format / Size | PDF / 271 Kb |
| Document Language | English |
AD7720 TIMING CHARACTERISTICS (AVDD = +5 V. 5%; DVDD = +5 V. 5%; AGND = DGND = 0 V, REF2= +2.5 V unless otherwise noted)
Model Line for this Datasheet
Text Version of Document
AD7720 TIMING CHARACTERISTICS (AVDD = +5 V
6
5%; DVDD = +5 V
6
5%; AGND = DGND = 0 V, REF2= +2.5 V unless otherwise noted) Limit at TMIN, TMAX Parameter (B Version) Units Conditions/Comments
fMCLK 100 kHz min Master Clock Frequency 15 MHz max 12.5 MHz for Specified Performance t1 67 ns min Master Clock Period t2 0.45 × tMCLK ns min Master Clock Input High Time t3 0.45 × tMCLK ns min Master Clock Input Low Time t4 15 ns min Data Hold Time After SCLK Rising Edge t5 10 ns min RESET Pulsewidth t6 10 ns min RESET Low Time Before MCLK Rising t7 20 × tMCLK ns max DVAL High Delay after RESET Low NOTE Guaranteed by design.
IOL 1.6mA TO OUTPUT +1.6V PIN CL 50pF IOH 200 A
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
t1 SCLK (O) t2 t3 t4 DATA (O) NOTE: O SIGNIFIES AN OUTPUT
Figure 3. Data Timing
MCLK (I) t6 RESET (I) t5 t7 DVAL (O) NOTE: I SIGNIFIES AN INPUT O SIGNIFIES AN OUTPUT
Figure 4. RESET Timing –4– REV. 0
6
5%; DVDD = +5 V
6
5%; AGND = DGND = 0 V, REF2= +2.5 V unless otherwise noted) Limit at TMIN, TMAX Parameter (B Version) Units Conditions/Comments
fMCLK 100 kHz min Master Clock Frequency 15 MHz max 12.5 MHz for Specified Performance t1 67 ns min Master Clock Period t2 0.45 × tMCLK ns min Master Clock Input High Time t3 0.45 × tMCLK ns min Master Clock Input Low Time t4 15 ns min Data Hold Time After SCLK Rising Edge t5 10 ns min RESET Pulsewidth t6 10 ns min RESET Low Time Before MCLK Rising t7 20 × tMCLK ns max DVAL High Delay after RESET Low NOTE Guaranteed by design.
IOL 1.6mA TO OUTPUT +1.6V PIN CL 50pF IOH 200 A
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
t1 SCLK (O) t2 t3 t4 DATA (O) NOTE: O SIGNIFIES AN OUTPUT
Figure 3. Data Timing
MCLK (I) t6 RESET (I) t5 t7 DVAL (O) NOTE: I SIGNIFIES AN INPUT O SIGNIFIES AN OUTPUT
Figure 4. RESET Timing –4– REV. 0
