Datasheet AD7819 (Analog Devices) - 10

AD7819 t1 t2 EXT CONVST t3 tPOWER-UP INT CONVST BUSY CS/RD DB7–DB0 8 MSBs
Figure 13. Mode 1 Operation
EXT CONVST tPOWER-UP t1 INT CONVST t3 BUSY CS/RD DB7–DB0 8 MSBs
Figure 14. Mode 2 Operation
PARALLEL INTERFACE
BUSY goes logic high. Care must be taken to ensure that a read The parallel interface of the AD7819 is eight bits wide. The out- operation does not occur while BUSY is high. Data read from put data buffers are activated when both CS and RD are logic the AD7819 while BUSY is high will be invalid. For optimum low. At this point the contents of the data register are placed on performance the read operation should end at least 100 ns (t the 8-bit data bus. Figure 15 shows the timing diagram for the par- 8) prior to the falling edge of the next CONVST. allel port. The Parallel Interface of the AD7819 is reset when
CONVST t2 t3 t8 BUSY t1 CS t4 t5 RD t7 t6 DB7–DB0 8 MSBs
Figure 15. Parallel Port Timing REV. B –9–