Datasheet AD9241 (Analog Devices) - 9

AD9241 INTRODUCTION
converter. Specifically, the input to the A/D core is the difference The AD9241 uses a four-stage pipeline architecture with a of the voltages applied at the VINA and VINB input pins. wideband input sample-and-hold amplifier (SHA) implemented Therefore, the equation, on a cost-effective CMOS process. Each stage of the pipeline, VCORE = VINA – VINB (1) excluding the last, consists of a low resolution flash A/D con- defines the output of the differential input stage and provides the nected to a switched capacitor DAC and interstage residue input to the A/D core. amplifier (MDAC). The residue amplifier amplifies the differ- ence between the reconstructed DAC output and the flash input The voltage, VCORE, must satisfy the condition, for the next stage in the pipeline. One bit of redundancy is used –VREF ≤ VCORE ≤ VREF (2) in each of the stages to facilitate digital correction of flash er- rors. The last stage simply consists of a flash A/D. where VREF is the voltage at the VREF pin. The pipeline architecture allows a greater throughput rate at the While an infinite combination of VINA and VINB inputs exist expense of pipeline delay or latency. This means that while the to satisfy Equation 2, an additional limitation is placed on the converter is capable of capturing a new input sample every clock inputs by the power supply voltages of the AD9241. The power cycle, it actually takes three clock cycles for the conversion to be supplies bound the valid operating range for VINA and VINB. fully processed and appear at the output. This latency is not a The condition, concern in most applications. The digital output, together with AVSS – 0.3 V < VINA < AVDD + 0.3 V (3) the out-of-range indicator (OTR), is latched into an output AVSS – 0.3 V < VINB < AVDD + 0.3 V buffer to drive the output pins. The output drivers can be con- figured to interface with +5 V or +3.3 V logic families. where AVSS is nominally 0 V and AVDD is nominally +5 V, defines this requirement. Thus, the range of valid inputs for The AD9241 uses both edges of the clock in its internal timing VINA and VINB is any combination that satisfies both Equa- circuitry (see Figure 1 and specification page for exact timing tions 2 and 3. requirements). The A/D samples the analog input on the rising edge of the clock input. During the clock low time (between the For additional information showing the relationship between falling edge and rising edge of the clock), the input SHA is in VINA, VINB, VREF and the digital output of the AD9241, see the sample mode; during the clock high time it is in the hold Table IV. mode. System disturbances just prior to the rising edge of the Refer to Table I and Table II for a summary of the various clock and/or excessive clock jitter may cause the input SHA to analog input and reference configurations
.
acquire the wrong value and should be minimized.
ANALOG INPUT OPERATION ANALOG INPUT AND REFERENCE OVERVIEW
Figure 21 shows the equivalent analog input of the AD9241, Figure 20, a simplified model of the AD9241, highlights the rela- which consists of a differential sample-and-hold amplifier tionship between the analog inputs, VINA, VINB, and the (SHA). The differential input structure of the SHA is highly reference voltage, VREF. Like the voltage applied to the top of flexible, allowing the devices to be easily configured for either a the resistor ladder in a flash A/D converter, the value VREF defines differential or single-ended input. The dc offset, or common- the maximum input voltage to the A/D core. The minimum input mode voltage, of the input(s) can be set to accommodate either voltage to the A/D core is automatically defined to be –VREF. single-supply or dual supply systems. Also, note that the analog inputs, VINA and VINB, are interchangeable, with the exception
AD9241
that reversing the inputs to the VINA and VINB pins results in a
VINA +VREF
polarity inversion.
VCORE A/D 14 CORE CH QS2 VINB –VREF C + PIN Q C C S1 S PAR VINA
Figure 20. Equivalent Functional Input Circuit
Q Q C H1 S1 S VINB C –
The addition of a differential input structure gives the user an
PIN C Q PAR S2
additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily config-
CH
ure the inputs for either single-ended operation or differential operation. The A/D’s input structure allows the dc offset of the input signal to be varied independently of the input span of the Figure 21. Simplified Input Circuit –8– REV. 0