Datasheet AD7810 (Analog Devices) - 7

AD7810 CIRCUIT DESCRIPTION SUPPLY 2.7V TO 5.5V TWO WIRE Converter Operation 10
␮
F 0.1
␮
F SERIAL
The AD7810 is a successive approximation analog-to-digital
INTERFACE
converter based around a charge redistribution DAC. The ADC
V V DD REF
can convert analog input signals in the range 0 V to V
0V TO VREF
DD. Fig-
V SCLK IN+ INPUT
ures 4 and 5 below show simplified schematics of the ADC.
V AD7810 D
␮
C/
␮
P IN– OUT
Figure 4 shows the ADC during its acquisition phase. SW2 is
AGND CONVST
closed and SW1 is in Position A; the comparator is held in a balanced condition; and the sampling capacitor acquires the signal on V Figure 6. Typical Connection Diagram IN+.
Analog Input CHARGE
Figure 7 shows an equivalent circuit of the analog input struc-
REDISTRIBUTION DAC
ture of the AD7810. The two diodes, D1 and D2, provide ESD
SAMPLING CAPACITOR
protection for the analog inputs. Care must be taken to ensure
A VIN+
that the analog input signal never exceeds the supply rails by
CONTROL SW1 LOGIC
more than 200 mV. This will cause these diodes to become
B ACQUISITION SW2 PHASE
forward biased and start conducting current into the substrate.
COMPARATOR CLOCK
The maximum current these diodes can conduct without caus-
VIN– VDD/3 OSC
ing irreversible damage to the part is 20 mA. The capacitor C2 Figure 4. ADC Acquisition Phase is typically about 4 pF and can be primarily attributed to pin capacitance. The resistor R1 is a lumped component made up of When the ADC starts a conversion (see Figure 5), SW2 will the on resistance of a multiplexer and a switch. This resistor is open and SW1 will move to Position B, causing the comparator typically about 125 Ω. The capacitor C1 is the ADC sampling to become unbalanced. The control logic and the charge redis- capacitor and has a capacitance of 3.5 pF. tribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator
V
back into a balanced condition. When the comparator is rebal-
DD
anced, the conversion is complete. The control logic generates
C1 R1 D1
the ADC output code. Figure 11 shows the ADC transfer function.
3.5pF 125
⍀
VIN+ VDD/3 C2 D2 4pF CHARGE REDISTRIBUTION CONVERT PHASE – SWITCH OPEN DAC ACQUISITION PHASE – SWITCH CLOSED SAMPLING CAPACITOR A
Figure 7. Equivalent Analog Input Circuit
VIN+ CONTROL SW1 LOGIC
The analog input of the AD7810 is made up of a pseudo differ-
B CONVERSION SW2 PHASE
ential pair. V
COMPARATOR
IN+ pseudo differential with respect to VIN–. The
CLOCK
signal is applied to V
V V
IN+, but in the pseudo differential scheme
IN– DD/3 OSC
the sampling capacitor is connected to VIN– during conversion Figure 5. ADC Conversion Phase (see Figure 8). This input scheme can be used to remove offsets that exist in a system. For example, if a system had an offset of
TYPICAL CONNECTION DIAGRAM
0.5 V, the offset could be applied to VIN– and the signal applied Figure 6 shows a typical connection diagram for the AD7810. The to VIN+. This has the effect of offsetting the input span by 0.5 V. serial interface is implemented using two wires; the rising edge It is only possible to offset the input span when the reference of CONVST enables the serial interface—see Serial Interface voltage (VREF) is less than VDD – VOFFSET. section for more details. VREF is connected to a well decoupled VDD pin to provide an analog input range of 0 V to VDD. When
CHARGE
V
REDISTRIBUTION
DD is first connected, the AD7810 powers up in a low current
DAC
mode, i.e., power-down. A rising edge on the CONVST input
SAMPLING COMPARATOR
will cause the part to power up—see Operating Modes. If power
CAPACITOR VIN+
consumption is of concern, the automatic power-down at the
CONTROL VIN(+) LOGIC
end of a conversion should be used to improve power perfor-
V CONVERSION OFFSET SW2 PHASE
mance. See Power vs. Throughput Rate section of the data sheet.
VIN– CLOCK VDD/3 OSC VOFFSET
Figure 8. Pseudo Differential Input Scheme –6– REV. B