Datasheet AD7862 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Simultaneous Sampling Dual 250 kSPS 12-Bit ADC |
| Pages / Page | 17 / 5 — AD7862. TIMING CHARACTERISTICS1, 2 DD = +5 V. 5%, AGND = DGND = 0 V, REF … |
| File Format / Size | PDF / 454 Kb |
| Document Language | English |
AD7862. TIMING CHARACTERISTICS1, 2 DD = +5 V. 5%, AGND = DGND = 0 V, REF = Internal. All Specifications TMIN to TMAX unless
Model Line for this Datasheet
Text Version of Document
AD7862 (V TIMING CHARACTERISTICS1, 2 DD = +5 V
6
5%, AGND = DGND = 0 V, REF = Internal. All Specifications TMIN to TMAX unless otherwise noted.) A, B S Parameter Versions Version Units Test Conditions/Comments
tCONV 3.6 3.6 µs max Conversion Time tACQ 0.3 0.3 us max Acquisition Time Parallel Interface t1 0 0 ns min CS to RD Setup Time t2 0 0 ns min CS to RD Hold Time t3 35 45 ns min CONVST Pulse Width t4 35 45 ns min Read Pulse Width t 3 5 12 12 ns min Data Access Time After Falling Edge of RD 60 70 ns max t 4 6 5 5 ns min Bus Relinquish Time After Rising Edge of RD 30 40 ns max t7 40 40 ns min Time Between Consecutive Reads NOTES 1Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V. 2 See Figure 1. 3Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice.
CONVST t3 BUSY tCONV A0 CS
... ...
t t 1 t2 7 t RD 4 t5 t6 DATA VA1 VA2 VB1 VB2
Figure 1. Timing Diagram
1.6mA TO OUTPUT +1.6V PIN 50pF 200µA
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.
WARNING!
Although the AD7862 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. 0
6
5%, AGND = DGND = 0 V, REF = Internal. All Specifications TMIN to TMAX unless otherwise noted.) A, B S Parameter Versions Version Units Test Conditions/Comments
tCONV 3.6 3.6 µs max Conversion Time tACQ 0.3 0.3 us max Acquisition Time Parallel Interface t1 0 0 ns min CS to RD Setup Time t2 0 0 ns min CS to RD Hold Time t3 35 45 ns min CONVST Pulse Width t4 35 45 ns min Read Pulse Width t 3 5 12 12 ns min Data Access Time After Falling Edge of RD 60 70 ns max t 4 6 5 5 ns min Bus Relinquish Time After Rising Edge of RD 30 40 ns max t7 40 40 ns min Time Between Consecutive Reads NOTES 1Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V. 2 See Figure 1. 3Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice.
CONVST t3 BUSY tCONV A0 CS
... ...
t t 1 t2 7 t RD 4 t5 t6 DATA VA1 VA2 VB1 VB2
Figure 1. Timing Diagram
1.6mA TO OUTPUT +1.6V PIN 50pF 200µA
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.
WARNING!
Although the AD7862 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. 0
