AD772264 CKLIN CYCLESCLKINSCO(CFMT = 0)32 SCO CYCLESFSO(SFMT = 0)SCOVALID DATA FOR 16 SCO CYCLESZERO FOR LAST 16 SCO CYCLESVALID Figure 2a. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE) 64 CKLIN CYCLESCLKINSCO(CFMT = 0)32 SCO CYCLESFSOLOW FOR 16 SCO CYCLES(SFMT = 1)HIGH FOR LAST 16 SCO CYCLESSCOVALID DATA FOR 16 SCO CYCLESZERO FOR LAST 16 SCO CYCLESVALID Figure 2b. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE) tt54t22.3VCLKIN0.8Vt3t1t8t6FSItt79SCOt9t10 Figure 3. Serial Mode Timing for Clock Input, Frame Sync Input, and Serial Clock Output CLKINt1FSIt10SCOt11t12SFMT = LOGICFSOLOW(0)t14SDOD15D14D13D1D0t13SCOt12t11SFMT = LOGICLOW FORFSOD15–D0HIGH(1)t13SDOD15D14D13D1D0 Figure 4. Serial Mode Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (CFMT = Logic Low, TSI = DOE) –6– REV. B Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING SPECIFICATIONS PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION PARALLEL MODE PIN FUNCTION DESCRIPTIONS SERIAL MODE PIN FUNCTION DESCRIPTIONS TERMINOLOGY Signal-to-Noise Plus Distortion Ratio (S/(N+D)) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Intermodulation Distortion Pass-Band Ripple Pass-Band Frequency Cutoff Frequency Stop-Band Frequency Stop-Band Attenuation Integral Nonlinearity Differential Nonlinearity Common-Mode Rejection Ratio Unipolar Offset Error Bipolar Offset Error Gain Error Typical Performance Characteristics CIRCUIT DESCRIPTION APPLYING THE AD7722 Analog Input Range Differential Inputs Applying the Reference Input Circuits Clock Generation Varying the Master Clock SYSTEM SYNCHRONIZATION AND CONTROL SYNC Input DVAL Reset Input Power-On Reset Offset and Gain Calibration DATA INTERFACING Parallel Interface SERIAL INTERFACE 2-Channel Multiplexed Operation Serial Interfacing to DSPs OUTLINE DIMENSIONS Revision History