Datasheet AD9057 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 8-Bit, 40/60/80 MSPS A/D Converter |
| Pages / Page | 13 / 10 — AD9057. ENCODE. 500. AIN. VREF IN. PWRDN. VDD, 3V TO 5V. D0–D7. BIAS OUT. … |
| Revision | D |
| File Format / Size | PDF / 361 Kb |
| Document Language | English |
AD9057. ENCODE. 500. AIN. VREF IN. PWRDN. VDD, 3V TO 5V. D0–D7. BIAS OUT. VREF OUT. 2.5k
Model Line for this Datasheet
Text Version of Document
AD9057
The power-down function of the AD9057 can be done through a oscilloscope or spectrum analyzer. The DAC converts the ADC’s board jumper connection. Connect E7 to E9 (5 V to PWRDN) for digital outputs to an analog signal for examination at the DAC power-down operation. For normal operation, connect E8 to E9 OUT connector. The DAC is clocked at the ADC encode (ground to PWRDN). frequency. The AD9760 is a 10-bit/100 MSPS single 5 V supply The encode signal source should be TTL/CMOS compatible and DAC. The reconstruction signal facilitates quick system trouble- capable of driving a 50 W termination (R7). The digital outputs shooting or confirmation of ADC functionality without requiring of the AD9057 are buffered through latches on the evaluation external digital memory, timing, or display interfaces. The DAC board (U3) and are available for the user at connector Pins 30 can be used for limited dynamic testing, but customers should note to 37. Latch timing is derived from the ADC encode clock and a that test results will be based on the combined performance of the digital clocking signal is provided for the board user at connector ADC and DAC (the best ADC performance will be recognized Pins 2 and 21. by evaluating the digital outputs of the ADC directly). An on-board reconstruction digital-to-analog converter is available for quick evaluations of ADC performance using an
VD VD ENCODE 500
⍀
AIN VREF IN PWRDN
Digital Inputs Analog Input
VDD, 3V TO 5V VD 1k
⍀
D0–D7 VREF IN BIAS OUT
Digital Outputs Bias Output
V V D D 3k
⍀
VREF OUT VREF IN 2.5k
⍀ VREF Output VREF Input Figure 6. Equivalent Circuits REV. D –9– Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics THEORY OF OPERATION USING THE AD9057 Analog Inputs Voltage Reference Digital Logic (5 V/3 V Systems) Timing Power Dissipation APPLICATIONS Evaluation Board OUTLINE DIMENSIONS Revision History
The power-down function of the AD9057 can be done through a oscilloscope or spectrum analyzer. The DAC converts the ADC’s board jumper connection. Connect E7 to E9 (5 V to PWRDN) for digital outputs to an analog signal for examination at the DAC power-down operation. For normal operation, connect E8 to E9 OUT connector. The DAC is clocked at the ADC encode (ground to PWRDN). frequency. The AD9760 is a 10-bit/100 MSPS single 5 V supply The encode signal source should be TTL/CMOS compatible and DAC. The reconstruction signal facilitates quick system trouble- capable of driving a 50 W termination (R7). The digital outputs shooting or confirmation of ADC functionality without requiring of the AD9057 are buffered through latches on the evaluation external digital memory, timing, or display interfaces. The DAC board (U3) and are available for the user at connector Pins 30 can be used for limited dynamic testing, but customers should note to 37. Latch timing is derived from the ADC encode clock and a that test results will be based on the combined performance of the digital clocking signal is provided for the board user at connector ADC and DAC (the best ADC performance will be recognized Pins 2 and 21. by evaluating the digital outputs of the ADC directly). An on-board reconstruction digital-to-analog converter is available for quick evaluations of ADC performance using an
VD VD ENCODE 500
⍀
AIN VREF IN PWRDN
Digital Inputs Analog Input
VDD, 3V TO 5V VD 1k
⍀
D0–D7 VREF IN BIAS OUT
Digital Outputs Bias Output
V V D D 3k
⍀
VREF OUT VREF IN 2.5k
⍀ VREF Output VREF Input Figure 6. Equivalent Circuits REV. D –9– Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics THEORY OF OPERATION USING THE AD9057 Analog Inputs Voltage Reference Digital Logic (5 V/3 V Systems) Timing Power Dissipation APPLICATIONS Evaluation Board OUTLINE DIMENSIONS Revision History
