Datasheet AD7891 (Analog Devices) - 9

AD7891 SERIAL INTERFACE MODE FUNCTIONS
When the part is configured for serial mode (MODE = 0), five of the 12 data input/output lines provide serial interface functions. These functions are outlined below.
PLCC Pin No. MQFP Pin No. Mnemonic Description
18 12 SCLK Serial Clock Input. This is an externally applied serial clock that is used to load serial data to the control register and to access data from the output register. 15 9 TFS Transmit Frame Synchronization Pulse. Active low logic input with serial data expected after the falling edge of this signal. 16 10 RFS Receive Frame Synchronization Pulse. This is an active low logic input with RFS provided externally as a strobe or framing pulse to access serial data from the output register. For applications that require that data be transmitted and received at the same time, RFS and TFS should be connected together. 21 15 DATA OUT Serial Data Output. Sixteen bits of serial data are provided with the data FORMAT bit and the three address bits of the control register preceding the 12 bits of conversion data. Serial data is valid on the falling edge of SCLK for 16 edges after RFS goes low. Output conversion data coding is twos complement when the FORMAT bit of the control register is 1 and straight binary when the FORMAT bit of the control register is 0. 17 11 DATA IN Serial Data Input. Serial data to be loaded to the control register is provided at this input. The first six bits of serial data are loaded to the control register on the first six falling edges of SCLK after TFS goes low. Serial data on subsequent SCLK edges is ignored while TFS remains low. 13, 14 7, 8 TEST Test Pin. When the device is configured for serial mode of operation, two of the pins which had been data inputs become test inputs. To ensure correct operation of the device, both TEST inputs should be tied to a logic low potential.
CONTROL REGISTER
The control register for the AD7891 contains six bits of information as described below. These six bits can be written to the control register either in a parallel mode write operation or via a serial mode write operation. The default (power-on) condition of all bits in the control register is 0. Six serial clock pulses must be provided to the part in order to write data to the control register. If TFS returns high before six serial clock cycles, no data transfer takes place to the control register and the write cycle has to be restarted to write data to the control register. However, if the SWCONV bit of the register was previously set to a Logic 1 and TFS is brought high before six serial clock cycles, another conversion is initiated.
B S L 0 B D ( ) 2 A 1 A 0 A S N O C W V S W S Y B T T A M R O F
A2 Address Input. This input is the most significant address input for multiplexer channel selection. A1 Address Input. This is the second most significant address input for multiplexer channel selection. A0 Address Input. Least significant address input for multiplexer channel selection. When the address is written to the control register, an internal pulse is initiated to allow for the multiplexer settling time and track/hold acquisi- tion time before the track/hold goes into hold and conversion is initiated. When the internal pulse times out, the track/hold goes into hold and conversion is initiated. The selected channel is given by the formula A2 ¥ 4 + A1 ¥ 2 + A0 + 1 SWCONV Conversion Start. Writing a 1 to this bit initiates a conversion in a similar manner to the CONVST input. Con- tinuous conversion starts do not take place when there is a 1 in this location. The internal pulse and the conver- sion process are initiated when a 1 is written to this bit. With a 1 in this bit, the hardware conversion start, i.e., the CONVST input, is disabled. Writing a 0 to this bit enables the hardware CONVST input. SWSTBY Standby Mode Input. Writing a 1 to this bit places the device in its standby or power-down mode. Writing a 0 to this bit places the device in its normal operating mode. FORMAT Data Format. Writing a 0 to this bit sets the conversion data output format to straight (natural) binary. This data format is generally used for unipolar input ranges. Writing a 1 to this bit sets the conversion data output format to twos complement. This output data format is generally used for bipolar input ranges. –8– REV. D Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS TIMING CHARACTERISTICS ORDERING GUIDE PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS PARALLEL INTERFACE MODE FUNCTIONS Data I/O Lines Parallel Read Operation SERIAL INTERFACE MODE FUNCTIONS CONTROL REGISTER TERMINOLOGY Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion Channel-to-Channel Isolation Relative Accuracy Differential Nonlinearity Positive Full-Scale Error (AD7891-1, ±10 V and ±5 V; AD7891-2, ±2.5 V) Positive Full-Scale Error (AD7891-2, 0 V to 5 V and 0 V to 2.5 V) Bipolar Zero Error (AD7891-1, ±10 V and ±5 V; AD7891-2, ±2.5 V) Unipolar Offset Error (AD7891-2, 0 V to 5 V and 0 V to 2.5 V) Negative Full-Scale Error (AD7891-1, ±10 V and ±5V; AD7891-2, ±2.5 V) Track/Hold Acquisition Time CONVERTER DETAILS INTERFACE INFORMATION Parallel Interface Mode Serial Interface Mode Simplifying the Serial Interface CIRCUIT DESCRIPTION Reference Analog Input Section Track/Hold Amplifier STANDBY Operation MICROPROCESSOR INTERFACING AD7891 to 8X51 Serial Interface AD7891 to 68HC11 Serial Interface AD7891 to ADSP-21xx Serial Interface AD7891 to DSP5600x Serial Interface AD7891 to TMS320xxx Serial Interface PARALLEL INTERFACING AD7891 to ADSP-21xx AD7891 to TMS32020, TMS320C25, and TMS320C5x AD7891 to TMS320C3x AD7891 to DSP5600x Power Supply Bypassing and Grounding AD7891 PERFORMANCE Linearity Noise Dynamic Performance Effective Number of Bits OUTLINE DIMENSIONS Revision History