Datasheet AD7714 (Analog Devices) - 4

AD7714 AD7714-3–SPECIFICATIONS (AVDD = +3.3␣ V, DVDD = +3.3␣ V, REF IN(+) = +1.25␣ V; REF␣ IN(–) = AGND; fCLK IN = 2.4576␣ MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.) Parameter A Versions Units Conditions/Comments
STATIC PERFORMANCE No Missing Codes 24 Bits min Guaranteed by Design. Bipolar Mode. For Filter Notches ≤ 60 Hz 22 Bits min For Filter Notch = 100 Hz 18 Bits min For Filter Notch = 250 Hz 15 Bits min For Filter Notch = 500 Hz 12 Bits min For Filter Notch = 1 kHz Output Noise See Tables I to IV Depends on Filter Cutoffs and Selected Gain Integral Nonlinearity ±0.0015 % of FSR max Filter Notches ≤ 60 Hz Unipolar Offset Error See Note 2 Unipolar Offset Drift3 0.4 µV/°C typ For Gains of 1, 2, 4 0.1 µV/°C typ For Gains of 8, 16, 32, 64, 128 Bipolar Zero Error See Note 2 Bipolar Zero Drift3 0.4 µV/°C typ For Gains of 1, 2, 4 0.1 µV/°C typ For Gains of 8, 16, 32, 64, 128 Positive Full-Scale Error4 See Note 2 Full-Scale Drift3, 5 0.4 µV/°C typ For Gains of 1, 2, 4 0.1 µV/°C typ For Gains of 8, 16, 32, 64, 128 Gain Error6 See Note 2 Gain Drift3, 7 0.2 ppm of FSR/°C typ Bipolar Negative Full-Scale Error ±0.003 % of FSR max Typically ± 0.0004% Bipolar Negative Full-Scale Drift3 1 µV/°C typ For Gains of 1, 2, 4 0.6 µV/°C typ For Gains of 8, 16, 32, 64, 128 ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN Unless Noted Input Common-Mode Rejection (CMR) 90 dB min At DC. Typically 102 dB. Normal-Mode 50 Hz Rejection8 100 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ± 0.02 × fNOTCH Normal-Mode 60 Hz Rejection8 100 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ± 0.02 × fNOTCH Common-Mode 50 Hz Rejection8 150 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ± 0.02 × fNOTCH Common-Mode 60 Hz Rejection8 150 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ± 0.02 × fNOTCH Common-Mode Voltage Range9 AGND to AVDD V min to V max AIN for BUFFER = 0 and REF IN Absolute AIN/REF IN Voltage9 AGND – 30 mV V min AIN for BUFFER = 0 and REF IN AVDD + 30 mV V max Absolute/Common-Mode AIN Voltage9 AGND + 50 mV V min BUFFER = 1 AVDD – 1.5 V V max AIN Input Current8 1 nA max AIN Sampling Capacitance8 7 pF max AIN Differential Voltage Range10 0 to +VREF/GAIN11 nom Unipolar Input Range (B/U Bit of Filter High Register = 1) ±VREF/GAIN nom Bipolar Input Range (B/U Bit of Filter High Register = 0) AIN Input Sampling Rate, fS GAIN × fCLK␣ IN/64 For Gains of 1, 2, 4 fCLK␣ IN/8 For Gains of 8, 16, 32, 64, 128 REF IN(+) – REF IN(–) Voltage +1.25 V nom ±1% for Specified Performance. Part Functions with Lower VREF REF IN Input Sampling Rate, fS fCLK IN/64 LOGIC INPUTS Input Current ±10 µA max All Inputs Except MCLK IN VINL, Input Low Voltage 0.4 V max VINH, Input High Voltage 2.0 V min MCLK IN Only VINL, Input Low Voltage 0.4 V max VINH, Input High Voltage 2.5 V min LOGIC OUTPUTS (Including MCLK OUT) VOL, Output Low Voltage 0.4 V max ISINK = 100␣ µA Except for MCLK OUT12 VOH, Output High Voltage DVDD – 0.6 V min ISOURCE = 100 µA Except for MCLK OUT12 Floating State Leakage Current ±10 µA max Floating State Output Capacitance13 9 pF typ Data Output Coding Binary Unipolar Mode Offset Binary Bipolar Mode NOTES 7Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero-scale calibrations only were performed as is the case with background calibration. 8These numbers are guaranteed by design and/or characterization. 9The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed. 10The input voltage range on the analog inputs is given here with respect to the voltage on the respective negative input of its differential or pseudo-differential pair. See Table VII for which inputs form differential pairs. 11VREF = REF IN(+) – REF IN(–). 12These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load. 13Sample tested at +25°C to ensure compliance. 14See Burnout Current section. REV. C –3–