Datasheet AD7892 (Analog Devices) - 10

AD7892 CIRCUIT DESCRIPTION
specified with a +2.5 V reference voltage. Errors in the refer- The AD7892 is a fast, 12-bit single supply A/D converter. It ence source will result in gain errors in the AD7892’s transfer provides the user with signal scaling, track/hold, reference, A/D function and will add to the specified full-scale errors on the converter and versatile interface logic functions on a single chip. part. On the AD7892-1 and AD7892-3, it will also result in an The signal scaling on the AD7892-1 allows the part to handle offset error injected in the attenuator stage. either ± 5 V or ± 10 V input signals while operating from a single The AD7892 contains an on-chip +2.5 V reference. To use this +5 V supply. The AD7892-2 handles a 0 V to +2.5 V analog reference as the reference source for the AD7892, simply con- input range, while signal scaling on the AD7892-3 allows it to nect a 0.1 µF disc ceramic capacitor from the REF OUT/ handle ±2.5 V input signals when operating from a single supply. REF IN pin to AGND. The voltage that appears at this pin is The part requires a +2.5 V reference which can be provided from internally buffered before being applied to the ADC. If this the part’s own internal reference or from an external reference reference is required for use external to the AD7892, it should source. be buffered as the part has a FET switch in series with the refer- Conversion is initiated on the AD7892 by pulsing the CONVST ence output resulting in a source impedance for this output of input. On the rising edge of CONVST, the track/hold goes 5.5 kΩ nominal. The tolerance on the internal reference is from track mode to hold mode and the conversion sequence is ±10 mV at 25°C with a typical temperature coefficient of started. At the end of conversion (falling edge of EOC), the 25 ppm/°C and a maximum error over temperature of ± 25 mV. track/hold returns to tracking mode and the acquisition time If the application requires a reference with a tighter tolerance or begins. Conversion time for the part is 1.47 µs (AD7892-3) and the AD7892 needs to be used with a system reference, then the the track/hold acquisition time is 200 ns (AD7892-3). This allows user has the option of connecting an external reference to this the AD7892-3 to operate at throughput rates up to 600 kSPS. REF OUT/REF IN pin. The external reference will effectively The AD7892-1 and AD7892-2 are specified with a 1.6 µs con- overdrive the internal reference and thus provide the reference version and 400 ns acquisition time allowing a throughput rate source for the ADC. The reference input is buffered before of 500 kSPS. being applied to the ADC with the maximum input current is
Track/Hold Section
±100 µA. Suitable reference sources for the AD7892 include the The track/hold amplifier on the AD7892 allows the ADC to AD680, AD780 and REF43 precision +2.5 V references. accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. The input bandwidth of the track/hold is greater
INTERFACING
than the Nyquist rate of the ADC even when the ADC is oper- The part provides two interface options, a 12-bit parallel inter- ated at its maximum throughput rate of 600 kHz (i.e., the track/ face and a three-wire serial interface. The required interface hold can handle input frequencies in excess of 300 kHz). mode is selected via the MODE pin. The two interface modes are discussed in the following sections. The track/hold amplifier acquires an input signal to 12-bit accu- racy in less than 200 ns. The operation of the track/hold is
Parallel Interface Mode
essentially transparent to the user. The track/hold amplifier The parallel interface mode is selected by tying the MODE goes from its tracking mode to its hold mode on the rising edge input to a logic high. Figure 2 shows a timing diagram illustrat- of CONVST. The aperture time for the track/hold (i.e., the ing the operational sequence of the AD7892. The on-chip delay time between the external CONVST signal and the track/ track/hold goes into hold mode, and conversion is initiated on hold actually going into hold) is typically 15 ns. At the end of the rising edge of the CONVST signal. When conversion is conversion, the part returns to its tracking mode. The acquisi- complete, the end of conversion line (EOC) pulses low to indi- tion time of the track/hold amplifier begins at this point. cate that new data is available in the AD7892’s output register. This EOC line can be used to drive an edge-triggered interrupt
Reference Section
of a microprocessor. The falling edge of the RD signal should The AD7892 contains a single reference pin, labelled REF OUT/ occur 200 ns prior to the next rising edge of CONVST. CS and REF IN, which either provides access to the part’s own +2.5 V RD going low accesses the 12-bit conversion result. In systems reference or to which an external +2.5 V reference can be con- where the part is interfaced to a gate array or ASIC, this EOC nected to provide the reference source for the part. The part is
CONVST (I) t tACQ 1 t2 EOC (O) tCONV t t9 3 CS (I) t4 t8 t5 RD (I) t7 t6 THREE-STATE VALID THREE-STATE DB0–DB11 (O) DATA NOTE: I = INPUT; O = OUTPUT
Figure 2. Parallel Mode Timing Diagram REV. C –9–