Datasheet AD7893 (Analog Devices) - 9

AD7893 CONVST 600ns MIN SCLK tCONVERT CONVERSION IS INITIATED CONVST INDICATES µP INT SERVICE SERIAL READ READ OPERATION AND TRACK/HOLD GOES TO µP THAT OR POLLING OPERATION SHOULD END 600ns INTO HOLD CONVERSION IS ROUTINE PRIOR TO NEXT COMPLETE RISING EDGE OF CONVST
Figure 4. CONVST Used as Status Signal This scheme limits the throughput rate to 12 µs minimum; how- clock, the AD7893 will start over again with outputting data ever, depending on the response time of the microprocessor to from its output register, and the data bus will no longer be the interrupt signal and the time taken by the processor to read three-stated even when the clock stops. Provided that the serial the data, this may be the fastest the system could have operated. clock has stopped before the next falling edge of CONVST, the In any case, the CONVST signal does not have to have a 50:50 AD7893 will continue to operate correctly with the output shift duty cycle. This can be tailored to optimize the throughput rate register being reset on the falling edge of CONVST; however, of the part for a given system. the SCLK line must be low when CONVST goes low in order Alternatively, the CONVST signal can be used as a normal narrow to reset the output shift register correctly. pulse width. The rising edge of CONVST can be used as an active The serial clock input does not have to be continuous during the high or rising edge-triggered interrupt. A software delay of 6 µs can serial read operation. The sixteen bits of data (four leading zeros then be implemented before data is read from the part. and 12 bit conversion result) can be read from the AD7893 in a
Serial Interface
number of bytes; however, the SCLR input must remain low be- The serial interface to the AD7893 consists of just two wires, a tween the two bytes. serial clock input (SCLK) and the serial data output (SDATA). Normally, the output register is updated at the end of conver- This allows for an easy to use interface to most microcontrollers, sion. If a serial read from the output register is in progress when DSP processors and shift registers. conversion is complete; however, the updating of the output Figure 5 shows the timing diagram for the read operation to the register is deferred. In this case, the output register is updated AD7893. The serial clock input (SCLK) provides the clock when the serial read is completed. If the serial read has not been source for the serial interface. Serial data is clocked out from the completed before the next falling edge of CONVST, the output SDATA line on the rising edge of this clock and is valid on the register will be updated on the falling edge of CONVST, and falling edge of SCLK. Sixteen clock pulses must be provided to the output shift register count is reset. In applications where the the part to access to full conversion result. The AD7893 pro- data read has been started and not completed before the falling vides four leading zeros followed by the 12-bit conversion result edge of CONVST, the user must provide a CONVST pulse starting with the MSB (DB11). The last data bit to be clocked width of greater than 1.5 µs to ensure correct setup of the AD7893 out on the final rising clock edge is the LSB (DB0). On the six- before the next conversion is initiated. In applications where the teenth falling edge of SCLK, the SDATA line is disabled (three- output update takes place either at the end of conversion or at stated). After this last bit has been clocked out, the SCLK input the end of a serial read that is completed 1.5 µs before the rising should return low and remain low until the next serial data read edge of CONVST, the normal pulse width of 50 ns minimum operation. If there are extra clock pulses after the sixteenth applies to CONVST.
t2 SCLK (I) t3 t t5 4 THREE-STATE THREE-STATE SDATA (O) FOUR LEADING ZEROS DB11 DB10 DB0
Figure 5. Data Read Operation –8– REV. E