Datasheet AD7712 (Analog Devices) - 3

AD7712–SPECIFICATIONS (AVDD = +5 V
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5%; DVDD = +5 V
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5%; VSS = 0 V or –5 V
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5%; REF IN(+) = +2.5 V; REF IN(–) = AGND; MCLK IN = 10 MHz unless otherwise stated. All specifications TMIN to TMAX, unless otherwise noted.) Parameter A, S Versions1 Unit Conditions/Comments
STATIC PERFORMANCE No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches ≤ 60 Hz 22 Bits min For Filter Notch = 100 Hz 18 Bits min For Filter Notch = 250 Hz 15 Bits min For Filter Notch = 500 Hz 12 Bits min For Filter Notch = 1 kHz Output Noise See Tables I and II Depends on Filter Cutoffs and Selected Gain Integral Nonlinearity @ 25°C ±0.0015 % FSR max Filter Notches ≤ 60 Hz TMIN to TMAX ±0.003 % FSR max Typically ± 0.0003% Positive Full-Scale Error2, 3, 4 Excluding Reference Full-Scale Drift5 1 µV/°C typ Excluding Reference. For Gains of 1, 2 0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128 Unipolar Offset Error2, 4 Unipolar Offset Drift5 0.5 µV/°C typ For Gains of 1, 2 0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128 Bipolar Zero Error2, 4 Bipolar Zero Drift5 0.5 µV/°C typ For Gains of 1, 2 0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128 Gain Drift 2 ppm/°C typ Bipolar Negative Full-Scale Error2 @ 25°C ±0.003 % FSR max Excluding Reference TMIN to TMAX ±0.006 % FSR max Typically ± 0.0006% Bipolar Negative Full-Scale Drift5 1 µV/°C typ Excluding Reference. For Gains of 1, 2 0.3 µV/°C typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128 ANALOG INPUTS/REFERENCE INPUTS Normal-Mode 50 Hz Rejection6 100 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 ⫻ fNOTCH Normal-Mode 60 Hz Rejection6 100 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 ⫻ fNOTCH AIN1/REF IN DC Input Leakage Current @ 25°C6 10 pA max TMIN to TMAX 1 nA max Sampling Capacitance6 20 pF max Common-Mode Rejection (CMR) 100 dB min At dc and AVDD = 5 V 90 dB min At dc and AVDD = 10 V Common-Mode 50 Hz Rejection6 150 dB min For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 ⫻ fNOTCH Common-Mode 60 Hz Rejection6 150 dB min For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 ⫻ fNOTCH Common-Mode Voltage Range7 VSS to AVDD V min to V max Analog Inputs8 Input Sampling Rate, fS See Table III AIN1 Input Voltage Range9 For Normal Operation. Depends on Gain Selected 0 V to V 10 REF V max Unipolar Input Range (B/U Bit of Control Register = 1) ±VREF V max Bipolar Input Range (B/U Bit of Control Register = 0) AIN2 Input Voltage Range9 For Normal Operation. Depends on Gain Selected 0 V to 4 ⫻ V 10 REF V max Unipolar Input Range (B/U Bit of Control Register = 1) ±4 ⫻ VREF V max Bipolar Input Range (B/U Bit of Control Register = 0) AIN2 DC Input Impedance 30 kΩ AIN2 Gain Error11 ±0.05 % typ Additional Error Contributed by Resistor Attenuator AIN2 Gain Drift 1 ppm/°C typ Additional Drift Contributed by Resistor Attenuator AIN2 Offset Error11 10 mV max Additional Error Contributed by Resistor Attenuator AIN2 Offset Drift 20 µV/°C typ Reference Inputs REF IN(+) – REF IN(–) Voltage12 2.5 to 5 V min to V max For Specified Performance. Part Is Functional with Lower VREF Voltages Input Sampling Rate, fS fCLK IN/256 NOTES 1Temperature range is as follows: A Version, –40°C to +85°C; S Version –55°C to +125°C. See also Note 18. 2Applies after calibration at the temperature of interest. 3Positive full-scale error applies to both unipolar and bipolar input ranges. 4These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration or background calibration. 5Recalibration at any temperature or use of the background calibration mode will remove these drift errors. 6These numbers are guaranteed by design and/or characterization. 7This common-mode voltage range is allowed, provided that the input voltage on AIN1(+) and AIN1(–) does not exceed AV DD + 30 mV and VSS – 30 mV. 8The AIN1 analog input presents a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended source resistance depends on the selected gain (see Tables IV and V). 9The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1(–) input. The input voltage range on the AIN2 input is with respect to AGND. The absolute voltage on the AIN1 input should not go more positive than AV DD + 30 mV or more negative than VSS – 30 mV. 10VREF = REF IN(+) – REF IN(–). 11This error can be removed using the system calibration capabilities of the AD7712. This error is not removed by the AD7712’s self-calibration features. The offset drift on the AIN2 input is 4 times the value given in the Static Performance section. 12The reference input voltage range may be restricted by the input voltage range requirement on the V BIAS input. –2– REV. F Document Outline ANALOG INPUT FUNCTIONS FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING CHARACTERISTICS PIN CONFIGURATION PIN FUNCTION DESCRIPTION TERMINOLOGY Integral Nonlinearity Positive Full-Scale Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span Control Register (24 Bits) Filter Selection (FS11–FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burnout Current Bipolar/Unipolar Inputs REFERENCE INPUT/OUTPUT VBIAS Input USING THE AD7712 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7712 to 8051 Interface AD7712 to 68HC11 Interface APPLICATIONS 4–20 mA LOOP OUTLINE DIMENSIONS Revision History