Datasheet AD7710 (Analog Devices) - 9

AD7710 Pin Mnemonic Function
19 TFS Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active after TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data-word is written to the part. 20 RFS Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the self-clocking mode, the SCLK and SDATA lines both become active after RFS goes low. In the external clocking mode, the SDATA line becomes active after RFS goes low. 21 DRDY Logic Output. A falling edge indicates that a new output word is available for transmission. The DRDY pin will return high upon completion of transmission of a full output word. DRDY is also used to indicate when the AD7710 has completed its on-chip calibration sequence. 22 SDATA Serial Data. Input/output with serial data being written to either the control register or the calibration regis- ters, and serial data being accessed from the control register, calibration registers, or the data register. During an output data read operation, serial data becomes active after RFS goes low (provided DRDY is low). During a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low. The output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs. 23 DVDD Digital Supply Voltage, 5 V. DVDD should not exceed AVDD by more than 0.3 V in normal operation. 24 DGND Ground Reference Point for Digital Circuitry.
Terminology Integral Nonlinearity Positive Full-Scale Overrange
This is the maximum deviation of any code from a straight line Positive full-scale overrange is the amount of overhead available passing through the endpoints of the transfer function. The to handle input voltages on AIN(+) input greater than AIN(–) + endpoints of the transfer function are zero scale (not to be con- VREF/GAIN (for example, noise peaks or excess voltages due to fused with bipolar zero), a point 0.5 LSB below the first code system gain errors in system calibration routines) without intro- transition (000 . 000 to 000 . 001) and full scale, a point ducing errors due to overloading the analog modulator or to 0.5 LSB above the last code transition (111 . 110 to 111 . overflowing the digital filter. 111). The error is expressed as a percentage of full scale.
Negative Full-Scale Overrange Positive Full-Scale Error
This is the amount of overhead available to handle voltages on Positive full-scale error is the deviation of the last code transi- AIN(+) below AIN(–) –VREF/GAIN without overloading the tion (111 . 110 to 111 . 111) from the ideal AIN(+) voltage analog modulator or overflowing the digital filter. Note that the (AIN(–) + VREF/GAIN – 3/2 LSBs). It applies to both unipolar analog input will accept negative voltage peaks even in the uni- and bipolar analog input ranges. polar mode provided that AIN(+) is greater than AIN(–) and greater than V
Unipolar Offset Error
SS – 30 mV. Unipolar offset error is the deviation of the first code transition
Offset Calibration Range
from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper- In the system calibration modes, the AD7710 calibrates its offset ating in the unipolar mode. with respect to the analog input. The offset calibration range specification defines the range of voltages that the AD7710 can
Bipolar Zero Error
This is the deviation of the midscale transition (0111 . 111 to accept and still calibrate offset accurately. 1000 . 000) from the ideal AIN(+) voltage (AIN(–) – 0.5 LSB)
Full-Scale Calibration Range
when operating in the bipolar mode. This is the range of voltages that the AD7710 can accept in the system calibration mode and still calibrate full scale correctly.
Bipolar Negative Full-Scale Error
This is the deviation of the first code transition from the ideal
Input Span
AIN(+) voltage (AIN(–) – VREF/GAIN + 0.5 LSB) when operat- In system calibration schemes, two voltages applied in sequence ing in the bipolar mode. to the AD7710’s analog input define the analog input range. The input span specification defines the minimum and maxi- mum input voltages from zero- to full-scale that the AD7710 can accept and still calibrate gain accurately. –8– REV. G Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS TIMING CHARACTERISTICS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Terminology Integral Nonlinearity Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span CONTROL REGISTER (24 BITS) PGA GAIN CHANNEL SELECTION Power-Down Word Length Output Compensation Current Burn-Out Current Bipolar/Unipolar Selection (Both Inputs) FILTER SELECTION (FS11–FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burnout Current Output Compensation Current Bipolar/Unipolar Inputs REFERENCE INPUT/OUTPUT VBIAS Input USING THE AD7710 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7710 to 8XC51 Interface AD7710 to 68HC11 Interface APPLICATIONS OUTLINE DIMENSIONS Revision History