Datasheet AD7701 (Analog Devices) - 10

AD7701 C
Figure 10 shows the filter frequency response. This is a six-pole
CLOCK
Gaussian response that provides 55 dB of 60 Hz rejection for a
R A
10 Hz cutoff frequency. If the clock frequency is halved to give a
IN
5 Hz cutoff, 60 Hz rejection is better than 90 dB. A normalized
TO DIGITAL FILTER
s-domain pole-zero plot of the filter is shown in Figure 11.
INTEGRATOR STROBED
The response of the filter is defined by:
COMPARATOR R
 −0 5 . 1 + 0. x 693 2 + 0. x 240 4 + 0. x 0555 6 +  H x ( ) =  
+VREF
 0. x  00962 8 + 0. x 00133 10 + 0. x 000154 12  
–VREF
where
1-BIT DAC
x = f f , f 409600 3 3 = f dB dB CLKIN Figure 9. SEC Basic Charge-Balancing ADC and f is the frequency of interest. The term charge-balancing comes from the fact that this system is a negative feedback loop that tries to keep the net charge on
20
the integrator capacitor at zero by balancing charge injected by the input voltage with charge injected by the 1-bit DAC. When
0 fCLK = 4MHz
the analog input is zero the only contribution to the integrator
–20
output comes from the 1-bit DAC. For the net charge on the integrator capacitor to be zero, the DAC output must spend half
–40
its time at +1 V and half its time at –1 V. Assuming ideal com-
–60 fCLK = 2MHz
ponents, the duty cycle of the comparator will be 50%.
–80
When a positive analog input is applied, the output of the 1-bit
GAIN – dBs
DAC must spend a larger proportion of the time at +1 V, so the
–100
duty cycle of the comparator increases. When a negative input
–120
voltage is applied, the duty cycle decreases.
fCLK = 1MHz –140
The AD7701 uses a second-order, sigma-delta modulator and a sophisticated digital filter that provides a rolling average of the
–1601 10 100
sampled output. After power-up or if there is a step change in
FREQUENCY – Hz
the input voltage, there is a settling time that must elapse before Figure 10. Frequency Response of AD7701 Filter valid data is obtained.
jw DIGITAL FILTERING j2
The AD7701’s digital filter behaves like an analog filter, with a few minor differences.
j1
First, since digital filtering occurs after the analog-to-digital
S1,2 = –1.4663 + j1.8191
conversion, it can remove noise injected during the conversion
s S3,4 = –1.7553 + j1.0005 0
process. Analog filtering cannot do this.
–2 –1 S5,6 = –1.8739 + j0.32272
On the other hand, analog filtering can remove noise super-
–j1
imposed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near full scale have the potential to saturate the analog modulator
–j2
and digital filter, even though the average value of the signal is within limits. To alleviate this problem, the AD7701 has over- Figure 11. Normalized Pole-Zero Plot of AD7701 Filter range headroom built into the sigma-delta modulator and digital Since the AD7701 contains this on-chip, low-pass filtering, filter that allows overrange excursions of 100 mV. If noise there is a settling time associated with step function inputs, signals are larger than this, consideration should be given to and data will be invalid after a step change until the settling analog input filtering, or to reducing the gain in the input time has elapsed. The AD7701 is, therefore, unsuitable for channel so that a full-scale input (2.5 V) gives only a half-scale high speed multiplexing, where channels are switched and input to the AD7701 (1.25 V). This will provide an overrange converted sequentially at high rates, as switching between chan- capability greater than 100% at the expense of reducing the nels can cause a step change in the input. Rather, it is intended dynamic range by one bit (50%). for distributed converter systems using one ADC per channel.
FILTER CHARACTERISTICS
However, slow multiplexing of the AD7701 is possible, pro- The cutoff frequency of the digital filter is f vided that the settling time is allowed to elapse before data for CLK/409600. At the maximum clock frequency of 4.096 MHz, the cutoff frequency the new channel is accessed. of the filter is 10 Hz and the output rate is 4 kHz. REV. E –9– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS TIMING CHARACTERISTICS DEFINITION OF TERMS Linearity Error Differential Linearity Error Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span GENERAL DESCRIPTION THEORY OF OPERATION DIGITAL FILTERING FILTER CHARACTERISTICS USING THE AD7701 SYSTEM DESIGN CONSIDERATIONS CLOCKING ANALOG INPUT RANGES INPUT SIGNAL CONDITIONING Source Resistance Antialias Considerations VOLTAGE REFERENCE CONNECTIONS GROUNDING AND SUPPLY DECOUPLING ACCURACY AND AUTOCALIBRATION CALIBRATION RANGE POWER-UP AND CALIBRATION POWER SUPPLY SEQUENCING GROUNDING SINGLE-SUPPLY OPERATION SLEEP MODE DIGITAL INTERFACE Synchronous Self-Clocking Mode (SSC) Synchronous External Clock Mode (SEC) Asynchronous Communications (AC) Mode DIGITAL NOISE AND OUTPUT LOADING OUTLINE DIMENSIONS Revision History