Datasheet AD7874 (Analog Devices) - 12
| Manufacturer | Analog Devices |
| Description | 4-channel Simultaneous Sampling, 12-Bit Data Acquisition System |
| Pages / Page | 17 / 12 — AD7874. AD7874–8086 Interface. AD7874–MC68000 Interface. ADDRESS BUS. … |
| Revision | C |
| File Format / Size | PDF / 454 Kb |
| Document Language | English |
AD7874. AD7874–8086 Interface. AD7874–MC68000 Interface. ADDRESS BUS. ADDR. 8086. DECODE. AD7874*. ALE. LATCH. CONVST. DB11. DB0. AD15. A15. TIMER
Model Line for this Datasheet
Text Version of Document
AD7874
Some applications may require that the conversion is initiated
AD7874–8086 Interface
by the microprocessor rather than an external timer. One option Figure 16 shows an interface between the AD7874 and the 8086 is to decode the AD7874 CONVST from the address bus so microprocessor. Unlike the previous interface examples, the that a write operation starts a conversion. Data is read at the microprocessor initiates conversion. This is achieved by gating end of the conversion sequence as before. Figure 16 shows an the 8086 WR signal with a decoded address output (different to example of initiating conversion using this method. Note that the AD7874 CS address). The AD7874 INT line is used to in- for all interfaces, a read operation should not be attempted dur- terrupt the microprocessor when the conversion sequence is ing conversion. completed. Data is read from the AD7874 using the following instruction:
AD7874–MC68000 Interface
An interface between the AD7874 and the MC68000 is shown MOV AX,ADC in Figure 15. As before, conversion is initiated using an external where AX is the 8086 accumulator and timer. The AD7874 INT line can be used to interrupt the pro- ADC is the AD7874 address. cessor or, alternatively, software delays can ensure that conver- sion has been completed before a read to the AD7874 is attempted. Because of the nature of its interrupts, the 68000
ADDRESS BUS
requires additional logic (not shown in Figure 15) to allow it to be interrupted correctly. For further information on 68000 in-
ADDR
terrupts, consult the 68000 users manual.
8086 DECODE CS
The MC68000 AS and R/W outputs are used to generate a separate RD input signal for the AD7874. CS is used to drive
AD7874* ALE LATCH
the 68000 DTACK input to allow the processor to execute a normal read operation to the AD7874. The conversion results
CONVST WR
are read using the following 68000 instruction:
RD RD
MOVE.W ADC,D0 where D0 is the 68000 D0 register and
DB11
ADC is the AD7874 address.
DB0 AD15 A15 TIMER ADDRESS/DATA BUS ADDRESS BUS AD0 A0 *ADDITIONAL PINS OMITTED FOR CLARITY ADDR CONVST
Figure 16. AD7874–8086 Interface
MC68000 DECODE CS EN DTACK AD7874* AS RD R/W DB11 DB0 D15 DATA BUS D0 *ADDITIONAL PINS OMITTED FOR CLARITY
Figure 15. AD7874–MC68000 Interface REV. C –11–
Some applications may require that the conversion is initiated
AD7874–8086 Interface
by the microprocessor rather than an external timer. One option Figure 16 shows an interface between the AD7874 and the 8086 is to decode the AD7874 CONVST from the address bus so microprocessor. Unlike the previous interface examples, the that a write operation starts a conversion. Data is read at the microprocessor initiates conversion. This is achieved by gating end of the conversion sequence as before. Figure 16 shows an the 8086 WR signal with a decoded address output (different to example of initiating conversion using this method. Note that the AD7874 CS address). The AD7874 INT line is used to in- for all interfaces, a read operation should not be attempted dur- terrupt the microprocessor when the conversion sequence is ing conversion. completed. Data is read from the AD7874 using the following instruction:
AD7874–MC68000 Interface
An interface between the AD7874 and the MC68000 is shown MOV AX,ADC in Figure 15. As before, conversion is initiated using an external where AX is the 8086 accumulator and timer. The AD7874 INT line can be used to interrupt the pro- ADC is the AD7874 address. cessor or, alternatively, software delays can ensure that conver- sion has been completed before a read to the AD7874 is attempted. Because of the nature of its interrupts, the 68000
ADDRESS BUS
requires additional logic (not shown in Figure 15) to allow it to be interrupted correctly. For further information on 68000 in-
ADDR
terrupts, consult the 68000 users manual.
8086 DECODE CS
The MC68000 AS and R/W outputs are used to generate a separate RD input signal for the AD7874. CS is used to drive
AD7874* ALE LATCH
the 68000 DTACK input to allow the processor to execute a normal read operation to the AD7874. The conversion results
CONVST WR
are read using the following 68000 instruction:
RD RD
MOVE.W ADC,D0 where D0 is the 68000 D0 register and
DB11
ADC is the AD7874 address.
DB0 AD15 A15 TIMER ADDRESS/DATA BUS ADDRESS BUS AD0 A0 *ADDITIONAL PINS OMITTED FOR CLARITY ADDR CONVST
Figure 16. AD7874–8086 Interface
MC68000 DECODE CS EN DTACK AD7874* AS RD R/W DB11 DB0 D15 DATA BUS D0 *ADDITIONAL PINS OMITTED FOR CLARITY
Figure 15. AD7874–MC68000 Interface REV. C –11–
