Datasheet AD7874 (Analog Devices) - 4

AD7874 (V TIMING CHARACTERISTICS1 DD = +5 V
6
5%, VSS = –5 V
6
5%, AGND = DGND = O V, tCLK = 2.5 MHz external unless otherwise noted.) Parameter A, B Versions S Version Units Conditions/Comments
t1 50 50 ns min CONVST Pulse Width t2 0 0 ns min CS to RD Setup Time t3
60 70
ns min RD Pulse Width t4 0 0 ns min CS to RD Hold Time t5 60 60 ns max RD to INT Delay t 2 6
57 70
ns max Data Access Time after RD t 3 7
5 5
ns min Bus Relinquish Time after RD
45 50
ns max t8 130 150 ns min Delay Time between Reads tCONV 31 31 µs min CONVST to INT, External Clock 32.5 32.5 µs max CONVST to INT, External Clock 31 31 µs min CONVST to INT, Internal Clock 35 35 µs max CONVST to INT, Internal Clock tCLK 10 10 µs max Minimum Input Clock Period NOTES 1Timing Specifications in
bold print
are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 2t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 3t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 7, quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice.
1.6mA ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted) VDD to AGND . –0.3 V to +7 V V
TO OUTPUT
DD to DGND . –0.3 V to +7 V
+2.1V PIN
V
50pF
SS to AGND . +0.3 V to –7 V AGND to DGND . –0.3 V to VDD + 0.3 V VIN to AGND . –15 V to +15 V REF OUT to AGND . 0 V to VDD
200
µ
A
Digital Inputs to DGND . –0.3 V to VDD + 0.3 V Digital Outputs to DGND . –0.3 V to V Figure 1. Load Circuit for Access Time DD + 0.3 V Operating Temperature Range Commercial (A, B Versions) . –40°C to +85°C
1.6mA
Extended (S Version) . –55°C to +125°C Storage Temperature Range . –65°C to +150°C
TO OUTPUT
Lead Temperature (Soldering, 10 secs) . +300°C
+2.1V PIN 50pF
Power Dissipation (Any Package) to +75°C . 1,000 mW Derates above +75°C by . 10 mW/°C
200
µ
A
*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the Figure 2. Load Circuit for Bus Relinquish Time operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.
WARNING!
Although the AD7874 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality. REV. C –3–