Datasheet AD5686, AD5684 (Analog Devices) - 10

AD5686/AD5684 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD5686/AD5684 B F SEL UT O RE ST ESET V V R R 16 15 14 13 V 1 12 SDIN OUTA GND 2 11 SYNC V 1 REF 16 RSTSEL V 3 10 SCLK DD V 2 OUTB 15 RESET V 4 9 V OUTC LOGIC AD5686/ V 3 OUTA 14 SDIN AD5684 5 6 7 8 GND 4 13 SYNC D IN TOP VIEW DO V 5 12 SCLK UT S DD (Not to Scale) O DAC GA V L V 6 OUTC 11 VLOGIC TOP VIEW (Not to Scale) V 7 OUTD 10 GAIN
006 007
NOTES SDO 8 9 LDAC 1. THE EXPOSED PAD MUST BE TIED TO GND.
10797- 10797- Figure 6. 16-Lead LFCSP Pin Configuration Figure 7. 16-Lead TSSOP Pin Configuration
Table 7. Pin Function Descriptions Pin No. LFCSP TSSOP Mnemonic Description
1 3 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 2 4 GND Ground Reference Point for All Circuitry on the Part. 3 5 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 4 6 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 5 7 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 6 8 SDO Serial Data Output. Can be used to daisy-chain a number of AD5686/AD5684 devices together or can be used for readback. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. 7 9 LDAC LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to be simultaneously updated. This pin can also be tied permanently low. 8 10 GAIN Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to VREF. When this pin is tied to VLOGIC, all four DAC outputs have a span from 0 V to 2 × VREF. 9 11 VLOGIC Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. 10 12 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. 11 13 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data is transferred in on the falling edges of the next 24 clocks. 12 14 SDIN Serial Data Input. These devices have a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. 13 15 RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. If the pin is forced low at power-up, the POR circuit does not initialize correctly until the pin is released. 14 16 RSTSEL Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to VLOGIC powers up all four DACs to midscale. 15 1 VREF Reference Input Voltage. 16 2 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND. Rev. C | Page 10 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER TRANSFER FUNCTION DAC ARCHITECTURE Output Amplifiers SERIAL INTERFACE Input Shift Register STANDALONE OPERATION WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDACB) Update DAC Register n with Contents of Input Register n Write to and Update DAC Channel n (Independent of LDACB) DAISY-CHAIN OPERATION READBACK OPERATION POWER-DOWN OPERATION LOAD DAC (HARDWARE LDACB PIN) Instantaneous DAC Updating (LDACB Held Low) Deferred DAC Updating (LDACB Is Pulsed Low) LDACB MASK REGISTER HARDWARE RESET (RESETB) RESET SELECT PIN (RSTSEL) APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING AD5686/AD5684 TO ADSP-BF531 INTERFACE AD5686/AD5684 TO SPORT INTERFACE LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE