Datasheet AD5381 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 40-Channel, 3 V/5 V, Single-Supply, 12-Bit, denseDAC |
| Pages / Page | 41 / 10 — Data Sheet. AD5381. TIMING CHARACTERISTICS SERIAL INTERFACE TIMING. Table … |
| Revision | E |
| File Format / Size | PDF / 865 Kb |
| Document Language | English |
Data Sheet. AD5381. TIMING CHARACTERISTICS SERIAL INTERFACE TIMING. Table 4. Parameter1. , 2. , 3. Limit at TMIN, TMAX. Unit
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Data Sheet AD5381 TIMING CHARACTERISTICS SERIAL INTERFACE TIMING
DVDD = 2.7 V to 5.5 V; AVDD= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. Parameter1 , 2 , 3 Limit at TMIN, TMAX Unit Description
t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min SYNC falling edge to SCLK falling edge setup time t5 4 13 ns min 24th SCLK falling edge to SYNC falling edge t6 4 33 ns min Minimum SYNC low time t7 10 ns min Minimum SYNC high time t7A 140 ns min Minimum SYNC high time in Readback mode t8 5 ns min Data setup time t9 4.5 ns min Data hold time t 4 10 36 ns max 24th SCLK falling edge to BUSY falling edge t11 670 ns max BUSY pulse width low (single channel update) t 4 12 20 ns min 24th SCLK falling edge to LDAC falling edge t13 20 ns min LDAC pulse width low t14 100/2000 ns min/max BUSY rising edge to DAC output response time t15 0 ns min BUSY rising edge to LDAC falling edge t16 100/2000 ns min/max LDAC falling edge to DAC output response time t17 3 µs typ DAC output settling time; boost mode off t18 20 ns min CLR pulse width low t19 40 µs max CLR pulse activation time t 5 20 30 ns max SCLK rising edge to SDO valid t 5 21 5 ns min SCLK falling edge to SYNC rising edge t 5 22 8 ns min SYNC rising edge to SCLK rising edge t23 20 ns min SYNC rising edge to LDAC falling edge 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and are timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, Figure 4, and Figure 5. 4 Standalone mode only. 5 Daisy-chain mode only.
200
µ
A IOL TO OUTPUT PIN VOH (MIN) OR C V L OL (MAX) 50pF 200
µ
A IOH
03732-002 Figure 2. Load Circuit for Digital Output Timing Rev. E | Page 9 of 40 Document Outline Features Integrated Functions Applications Functional Block Diagram Table Of Contents Revision History General Description Specifications AD5381-5 Specifications AD5381-3 Specifications AC Characteristics Timing Characteristics Serial Interface Timing I2C Serial Interface Timing Parallel Interface Timing Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Functional Description DAC Architecture—General Data Decoding On-Chip Special Function Registers (SFR) SFR Commands NOP (No Operation) Write CLR Code Soft CLR Soft Power-Down Soft Power-Up Soft RESET Control Register Write/Read Control Register Contents Channel Monitor Function Hardware Functions Reset Function Asynchronous Clear Function BUSY\ and LDAC\ Functions FIFO Operation in Parallel Mode Power-On Reset Power-Down Interfaces DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces Standalone Mode Daisy-Chain Mode Readback Mode I2C Serial Interface I2C Data Transfer START and STOP Conditions Repeated START Conditions Acknowledge Bit (ACK) AD5381 Slave Addresses Write Operation 4-Byte Mode 3-Byte Mode 2-Byte Mode Parallel Interface CS\ Pin WR\ Pin REG0, REG1 Pins Pin A5 to Pin A0 Pin DB11 to Pin DB0 Microprocessor Interfacing Parallel Interface AD5381 to MC68HC11 AD5381 to PIC16C6x/7x AD5381 to 8051 AD5381 to ADSP-BF527 Applications Information Power Supply Decoupling Power Supply Sequencing Typical Configuration Circuit Monitor Function Toggle Mode Function Thermal Monitor Function Optical Attenuators Utilizing FIFO Outline Dimensions Ordering Guide
Data Sheet AD5381 TIMING CHARACTERISTICS SERIAL INTERFACE TIMING
DVDD = 2.7 V to 5.5 V; AVDD= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. Parameter1 , 2 , 3 Limit at TMIN, TMAX Unit Description
t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min SYNC falling edge to SCLK falling edge setup time t5 4 13 ns min 24th SCLK falling edge to SYNC falling edge t6 4 33 ns min Minimum SYNC low time t7 10 ns min Minimum SYNC high time t7A 140 ns min Minimum SYNC high time in Readback mode t8 5 ns min Data setup time t9 4.5 ns min Data hold time t 4 10 36 ns max 24th SCLK falling edge to BUSY falling edge t11 670 ns max BUSY pulse width low (single channel update) t 4 12 20 ns min 24th SCLK falling edge to LDAC falling edge t13 20 ns min LDAC pulse width low t14 100/2000 ns min/max BUSY rising edge to DAC output response time t15 0 ns min BUSY rising edge to LDAC falling edge t16 100/2000 ns min/max LDAC falling edge to DAC output response time t17 3 µs typ DAC output settling time; boost mode off t18 20 ns min CLR pulse width low t19 40 µs max CLR pulse activation time t 5 20 30 ns max SCLK rising edge to SDO valid t 5 21 5 ns min SCLK falling edge to SYNC rising edge t 5 22 8 ns min SYNC rising edge to SCLK rising edge t23 20 ns min SYNC rising edge to LDAC falling edge 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and are timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, Figure 4, and Figure 5. 4 Standalone mode only. 5 Daisy-chain mode only.
200
µ
A IOL TO OUTPUT PIN VOH (MIN) OR C V L OL (MAX) 50pF 200
µ
A IOH
03732-002 Figure 2. Load Circuit for Digital Output Timing Rev. E | Page 9 of 40 Document Outline Features Integrated Functions Applications Functional Block Diagram Table Of Contents Revision History General Description Specifications AD5381-5 Specifications AD5381-3 Specifications AC Characteristics Timing Characteristics Serial Interface Timing I2C Serial Interface Timing Parallel Interface Timing Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Functional Description DAC Architecture—General Data Decoding On-Chip Special Function Registers (SFR) SFR Commands NOP (No Operation) Write CLR Code Soft CLR Soft Power-Down Soft Power-Up Soft RESET Control Register Write/Read Control Register Contents Channel Monitor Function Hardware Functions Reset Function Asynchronous Clear Function BUSY\ and LDAC\ Functions FIFO Operation in Parallel Mode Power-On Reset Power-Down Interfaces DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces Standalone Mode Daisy-Chain Mode Readback Mode I2C Serial Interface I2C Data Transfer START and STOP Conditions Repeated START Conditions Acknowledge Bit (ACK) AD5381 Slave Addresses Write Operation 4-Byte Mode 3-Byte Mode 2-Byte Mode Parallel Interface CS\ Pin WR\ Pin REG0, REG1 Pins Pin A5 to Pin A0 Pin DB11 to Pin DB0 Microprocessor Interfacing Parallel Interface AD5381 to MC68HC11 AD5381 to PIC16C6x/7x AD5381 to 8051 AD5381 to ADSP-BF527 Applications Information Power Supply Decoupling Power Supply Sequencing Typical Configuration Circuit Monitor Function Toggle Mode Function Thermal Monitor Function Optical Attenuators Utilizing FIFO Outline Dimensions Ordering Guide
