Datasheet ADA4930-1/ADA4930-2 (Analog Devices) - 7

ManufacturerAnalog Devices
DescriptionUltralow Noise Drivers for Low Voltage ADCs
Pages / Page25 / 7 — Data Sheet. ADA4930-1/ADA4930-2. ABSOLUTE MAXIMUM RATINGS Table 7. …
RevisionD
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Document LanguageEnglish

Data Sheet. ADA4930-1/ADA4930-2. ABSOLUTE MAXIMUM RATINGS Table 7. Parameter. Rating. THERMAL RESISTANCE. 3.5. ) 3.0 (W N

Data Sheet ADA4930-1/ADA4930-2 ABSOLUTE MAXIMUM RATINGS Table 7 Parameter Rating THERMAL RESISTANCE 3.5 ) 3.0 (W N

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Data Sheet ADA4930-1/ADA4930-2 ABSOLUTE MAXIMUM RATINGS Table 7.
The power dissipated in the package (PD) is the sum of the
Parameter Rating
quiescent power dissipation and the power dissipated in the package due to the load drive. The quiescent power is the voltage Supply Voltage 5.5 V between the supply pins (V Power Dissipation See Figure 4 S) times the quiescent current (IS). The power dissipated due to the load drive depends upon the Storage Temperature Range −65°C to +125°C particular application. The power due to load drive is calculated Operating Temperature Range −40°C to +105°C by multiplying the load current by the associated voltage drop Lead Temperature (Soldering, 10 sec) 300°C across the device. RMS voltages and currents must be used in Junction Temperature 150°C these calculations. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Airflow increases heat dissipation, effectively reducing θJA. In stress rating only; functional operation of the product at these addition, more metal directly in contact with the package leads/ or any other conditions above those indicated in the operational exposed pad from metal traces, through holes, ground, and section of this specification is not implied. Operation beyond power planes reduces θJA. the maximum operating conditions for extended periods may Figure 4 shows the maximum safe power dissipation vs. the affect product reliability. ambient temperature for the ADA4930-1 single 16-lead LFCSP
THERMAL RESISTANCE
(98°C/W) and the ADA4930-2 dual 24-lead LFCSP (67°C/W) on a JEDEC standard 4-layer board. θJA is specified for the device (including exposed pad) soldered
3.5
to a high thermal conductivity 2s2p circuit board, as described in EIA/JESD51-7.
) 3.0 (W N Table 8. Thermal Resistance IO T 2.5 Package Type θ PA JA Unit ADA4930-2 2.0
16-Lead LFCSP (Exposed Pad) 98 °C/W
ISSI D
24-Lead LFCSP (Exposed Pad) 67 °C/W
ER W 1.5 ADA4930-1 M PO MAXIMUM POWER DISSIPATION 1.0 MU XI
The maximum safe power dissipation in the ADA4930-1/
MA 0.5
ADA4930-2 packages is limited by the associated rise in junction temperature (T
0
J) on the die. At approximately 150°C,
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110
004 which is the glass transition temperature, the plastic changes its
TEMPERATURE (°C)
09209- properties. Even temporarily exceeding this temperature limit Figure 4. Maximum Power Dissipation vs. Ambient Temperature, can change the stresses that the package exerts on the die, 4-Layer Board permanently shifting the parametric performance of the
ESD CAUTION
ADA4930-1/ADA4930-2. Exceeding a junction temperature of 150°C for an extended period can result in changes in the silicon devices, potentially causing failure. Rev. C | Page 7 of 25 Document Outline Features Applications General Description Functional Block Diagrams Revision History Specifications 3.3 V Operation 3.3 V VOCM to VO, cm Performance 3.3 V General Performance 5 V Operation 5 V VOCM to VO, cm Performance 5 V General Performance Absolute Maximum Ratings Thermal Resistance Maximum Power Dissipation ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Operational Description Definition of Terms Differential Voltage Common-Mode Voltage Balance Theory of Operation Analyzing an Application Circuit Setting the Closed-Loop Gain Estimating the Output Noise Voltage Impact of Mismatches in the Feedback Networks Input Common-Mode Voltage Range Minimum RG Value Setting the Output Common-Mode Voltage Calculating the Input Impedance for an Application Circuit Terminating a Single-Ended Input Terminating a Single-Ended Input in a Single-Supply Applications Input Common-Mode Adjustment with DC Biased Source Input Common-Mode Adjustment with Resistors Layout, Grounding, and Bypassing High Performance ADC Driving Outline Dimensions Ordering Guide