Datasheet ADA4939-1/ADA4939-2 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Ultralow Distortion Differential ADC Driver |
| Pages / Page | 24 / 7 — Data Sheet. ADA4939-1/ADA4939-2. ABSOLUTE MAXIMUM RATINGS Table 7. … |
| Revision | A |
| File Format / Size | PDF / 597 Kb |
| Document Language | English |
Data Sheet. ADA4939-1/ADA4939-2. ABSOLUTE MAXIMUM RATINGS Table 7. Parameter. Rating. 3.0. THERMAL RESISTANCE. 2.5. ( N. ADA4939-2. 2.0. ISSI
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Data Sheet ADA4939-1/ADA4939-2 ABSOLUTE MAXIMUM RATINGS Table 7.
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the
Parameter Rating
package due to the load drive. The quiescent power is the voltage Supply Voltage 5.5 V between the supply pins (V Power Dissipation See Figure 4 S) times the quiescent current (IS). The power dissipated due to the load drive depends upon the Input Current, +IN, −IN, PD ±5 mA particular application. Calculate the power due to the load drive Storage Temperature Range −65°C to +125°C by multiplying the load current by the associated voltage drop Operating Temperature Range across the device. RMS voltages and currents must be used in ADA4939-1 −40°C to +105°C these calculations. ADA4939-2 −40°C to +105°C Lead Temperature (Soldering, 10 sec) 300°C Airflow increases heat dissipation, effectively reducing θJA. In Junction Temperature 150°C addition, more metal directly in contact with the package leads/ exposed pad from metal traces, through holes, ground, and power Stresses at or above those listed under Absolute Maximum planes reduces θJA. Ratings may cause permanent damage to the product. This is a Figure 4 shows the maximum safe power dissipation in the stress rating only; functional operation of the product at these package vs. the ambient temperature for the single 16-lead or any other conditions above those indicated in the operational LFCSP (98°C/W) and the dual 24-lead LFCSP (67°C/W) on a section of this specification is not implied. Operation beyond JEDEC standard 4-layer board with the exposed pad soldered to the maximum operating conditions for extended periods may a PCB pad that is connected to a solid plane. affect product reliability.
3.0 THERMAL RESISTANCE )
θ
W 2.5
JA is specified for the device (including exposed pad) soldered
( N
to a high thermal conductivity 2s2p circuit board, as described
IO ADA4939-2 T
in EIA/JESD 51-7.
2.0 PA ISSI Table 8. Thermal Resistance D 1.5 ER Package Type θ W ADA4939-1 JA Unit PO
ADA4939-1, 16-Lead LFCSP (Exposed Pad) 98 °C/W
1.0 M U
ADA4939-2, 24-Lead LFCSP (Exposed Pad) 67 °C/W
M XI A 0.5 M MAXIMUM POWER DISSIPATION 0
The maximum safe power dissipation for the ADA4939-1/
–40 –20 0 20 40 60 80 100
04 0 9- ADA4939-2 package is limited by the associated rise in junction
AMBIENT TEMPERATURE (°C)
42 07 temperature (T Figure 4. Maximum Power Dissipation vs. Ambient Temperature for J) on the die. At approximately 150°C, which is a 4-Layer Board the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently
ESD CAUTION
shifting the parametric performance of the ADA4939-1/ ADA4939-2. Exceeding a junction temperature of 150°C for an extended period can result in changes in the silicon devices, potentially causing failure. Rev. A | Page 7 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 5 V OPERATION ±DIN to VOUT, dm Performance VOCM to VOUT, cm Performance General Performance 3.3 V OPERATION ±DIN to VOUT, dm Performance VOCM to VOUT, cm Performance General Performance ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS OPERATIONAL DESCRIPTION DEFINITION OF TERMS Differential Voltage Common-Mode Voltage Balance THEORY OF OPERATION ANALYZING AN APPLICATION CIRCUIT SETTING THE CLOSED-LOOP GAIN STABLE FOR GAINS ≥2 ESTIMATING THE OUTPUT NOISE VOLTAGE IMPACT OF MISMATCHES IN THE FEEDBACK NETWORKS CALCULATING THE INPUT IMPEDANCE FOR AN APPLICATION CIRCUIT Terminating a Single-Ended Input INPUT COMMON-MODE VOLTAGE RANGE INPUT AND OUTPUT CAPACITIVE AC COUPLING MINIMUM RG VALUE OF 50 Ω SETTING THE OUTPUT COMMON-MODE VOLTAGE LAYOUT, GROUNDING, AND BYPASSING HIGH PERFORMANCE ADC DRIVING OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADA4939-1/ADA4939-2 ABSOLUTE MAXIMUM RATINGS Table 7.
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the
Parameter Rating
package due to the load drive. The quiescent power is the voltage Supply Voltage 5.5 V between the supply pins (V Power Dissipation See Figure 4 S) times the quiescent current (IS). The power dissipated due to the load drive depends upon the Input Current, +IN, −IN, PD ±5 mA particular application. Calculate the power due to the load drive Storage Temperature Range −65°C to +125°C by multiplying the load current by the associated voltage drop Operating Temperature Range across the device. RMS voltages and currents must be used in ADA4939-1 −40°C to +105°C these calculations. ADA4939-2 −40°C to +105°C Lead Temperature (Soldering, 10 sec) 300°C Airflow increases heat dissipation, effectively reducing θJA. In Junction Temperature 150°C addition, more metal directly in contact with the package leads/ exposed pad from metal traces, through holes, ground, and power Stresses at or above those listed under Absolute Maximum planes reduces θJA. Ratings may cause permanent damage to the product. This is a Figure 4 shows the maximum safe power dissipation in the stress rating only; functional operation of the product at these package vs. the ambient temperature for the single 16-lead or any other conditions above those indicated in the operational LFCSP (98°C/W) and the dual 24-lead LFCSP (67°C/W) on a section of this specification is not implied. Operation beyond JEDEC standard 4-layer board with the exposed pad soldered to the maximum operating conditions for extended periods may a PCB pad that is connected to a solid plane. affect product reliability.
3.0 THERMAL RESISTANCE )
θ
W 2.5
JA is specified for the device (including exposed pad) soldered
( N
to a high thermal conductivity 2s2p circuit board, as described
IO ADA4939-2 T
in EIA/JESD 51-7.
2.0 PA ISSI Table 8. Thermal Resistance D 1.5 ER Package Type θ W ADA4939-1 JA Unit PO
ADA4939-1, 16-Lead LFCSP (Exposed Pad) 98 °C/W
1.0 M U
ADA4939-2, 24-Lead LFCSP (Exposed Pad) 67 °C/W
M XI A 0.5 M MAXIMUM POWER DISSIPATION 0
The maximum safe power dissipation for the ADA4939-1/
–40 –20 0 20 40 60 80 100
04 0 9- ADA4939-2 package is limited by the associated rise in junction
AMBIENT TEMPERATURE (°C)
42 07 temperature (T Figure 4. Maximum Power Dissipation vs. Ambient Temperature for J) on the die. At approximately 150°C, which is a 4-Layer Board the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently
ESD CAUTION
shifting the parametric performance of the ADA4939-1/ ADA4939-2. Exceeding a junction temperature of 150°C for an extended period can result in changes in the silicon devices, potentially causing failure. Rev. A | Page 7 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 5 V OPERATION ±DIN to VOUT, dm Performance VOCM to VOUT, cm Performance General Performance 3.3 V OPERATION ±DIN to VOUT, dm Performance VOCM to VOUT, cm Performance General Performance ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS OPERATIONAL DESCRIPTION DEFINITION OF TERMS Differential Voltage Common-Mode Voltage Balance THEORY OF OPERATION ANALYZING AN APPLICATION CIRCUIT SETTING THE CLOSED-LOOP GAIN STABLE FOR GAINS ≥2 ESTIMATING THE OUTPUT NOISE VOLTAGE IMPACT OF MISMATCHES IN THE FEEDBACK NETWORKS CALCULATING THE INPUT IMPEDANCE FOR AN APPLICATION CIRCUIT Terminating a Single-Ended Input INPUT COMMON-MODE VOLTAGE RANGE INPUT AND OUTPUT CAPACITIVE AC COUPLING MINIMUM RG VALUE OF 50 Ω SETTING THE OUTPUT COMMON-MODE VOLTAGE LAYOUT, GROUNDING, AND BYPASSING HIGH PERFORMANCE ADC DRIVING OUTLINE DIMENSIONS ORDERING GUIDE
