Datasheet AD8556 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Digitally Programmable Sensor Signal Amplifier with EMI Filters |
| Pages / Page | 28 / 9 — AD8556. Data Sheet. VSS. NC 1. 12 VOUT. FILT/DIGOUT 2. 11 NC. AD8556 TOP … |
| Revision | B |
| File Format / Size | PDF / 728 Kb |
| Document Language | English |
AD8556. Data Sheet. VSS. NC 1. 12 VOUT. FILT/DIGOUT 2. 11 NC. AD8556 TOP VIEW. NC 3. 10 VCLAMP. DIGIN 4. VPO. NOTES 1. NC = NO CONNECT
Text Version of Document
AD8556 Data Sheet DD DD V VSS VSS A DV A D 16 15 14 13 NC 1 12 VOUT FILT/DIGOUT 2 11 NC AD8556 TOP VIEW NC 3 10 VCLAMP DIGIN 4 9 NC 5 6 7 8 S NC EG NC VN VPO NOTES 1. NC = NO CONNECT.
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2. THE EXPOSED PAD MUST BE CONNECTED TO DVSS (PIN 13).
05448- Figure 3. 16-Lead LFCSP_WQ Pin Configuration
Table 5. 16-Lead LFCSP_WQ Pin Function Descriptions LFCSP_WQ Mnemonic Description
0 EPAD Exposed Pad. The exposed pad must be connected to DVSS (Pin 13). 1, 3, 5, 7, 9, 11 NC Do Not Connect. 2 FILT/DIGOUT Unbuffered Amplifier Output in Series with a Resistor RF. Adding a capacitor between FILT and VDD or VSS implements a low-pass filtering function. In read mode, this pin functions as a digital output. 4 DIGIN Digital Input. 6 VNEG Negative Amplifier Input (Inverting Input). 8 VPOS Positive Amplifier Input (Noninverting Input). 10 VCLAMP Set Clamp Voltage at Output. 12 VOUT Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT pin. In read mode, VOUT is a buffered digital output. VSS Negative Supply Voltage. 13, 14 DVSS, AVSS Negative Supply Voltage. 15, 16 DVDD, AVDD Positive Supply Voltage. Rev. B | Page 8 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN VALUES OPEN WIRE FAULT DETECTION SHORTED WIRE FAULT DETECTION FLOATING VPOS, VNEG, OR VCLAMP FAULT DETECTION DEVICE PROGRAMMING Digital Interface Initial State Simulation Mode Programming Mode Parity Error Detection Read Mode Sense Current Programming Procedure Determining Optimal Gain and Offset Codes EMI/RFI PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
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2. THE EXPOSED PAD MUST BE CONNECTED TO DVSS (PIN 13).
05448- Figure 3. 16-Lead LFCSP_WQ Pin Configuration
Table 5. 16-Lead LFCSP_WQ Pin Function Descriptions LFCSP_WQ Mnemonic Description
0 EPAD Exposed Pad. The exposed pad must be connected to DVSS (Pin 13). 1, 3, 5, 7, 9, 11 NC Do Not Connect. 2 FILT/DIGOUT Unbuffered Amplifier Output in Series with a Resistor RF. Adding a capacitor between FILT and VDD or VSS implements a low-pass filtering function. In read mode, this pin functions as a digital output. 4 DIGIN Digital Input. 6 VNEG Negative Amplifier Input (Inverting Input). 8 VPOS Positive Amplifier Input (Noninverting Input). 10 VCLAMP Set Clamp Voltage at Output. 12 VOUT Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT pin. In read mode, VOUT is a buffered digital output. VSS Negative Supply Voltage. 13, 14 DVSS, AVSS Negative Supply Voltage. 15, 16 DVDD, AVDD Positive Supply Voltage. Rev. B | Page 8 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN VALUES OPEN WIRE FAULT DETECTION SHORTED WIRE FAULT DETECTION FLOATING VPOS, VNEG, OR VCLAMP FAULT DETECTION DEVICE PROGRAMMING Digital Interface Initial State Simulation Mode Programming Mode Parity Error Detection Read Mode Sense Current Programming Procedure Determining Optimal Gain and Offset Codes EMI/RFI PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
