Datasheet AD641 (Analog Devices) - 7

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AD641 CIRCUIT DESCRIPTION LOG OUT LOG COM
The AD641 uses five cascaded limiting amplifiers to approxi-
Q9
mate a logarithmic response to an input signal of wide dynamic
Q10 COMMON
range and wide bandwidth. This type of logarithmic amplifier
R3 R4 75
V
75 Q1
V has traditionally been assembled from several small scale ICs
SIG SIG
and numerous external components. The performance of these
IN Q2 OUT
semidiscrete circuits is often unsatisfactory. In particular, the logarithmic slope and intercept (see FUNDAMENTALS OF
R1
LOGARITHMIC CONVERSION) are usually not very stable
R2 85
V
85
V in the presence of supply and temperature variations even after
Q3 Q4 Q5 Q6 Q7 Q8
laborious and expensive individual calibration. The AD641 em- ploys high precision analog circuit techniques to ensure stability of scaling over wide variations in supply voltage and tempera-
–VS
ture. Laser trimming, using ac stimuli and operating conditions
1.09mA 1.09mA 565
m
A 565
m
A 2.18mA
similar to those encountered in practice, provides fully cali-
PTAT PTAT PTAT
brated logarithmic conversion. Figure 16. Simplified Schematic of a Single AD641 Stage Each of the amplifier/limiter stages in the AD641 has a small By summing the signals at the output of the detectors, a good signal voltage gain of 10 dB (×3.162) and a –3 dB bandwidth of approximation to a logarithmic transfer function can be achieved. 350 MHz. Fully differential direct coupling is used throughout. The lower the stage gain, the more accurate the approximation, This eliminates the many interstage coupling capacitors usually but more stages are then needed to cover a given dynamic range. required in ac applications, and simplifies low frequency signal The choice of 10 dB results in a theoretical periodic deviation or processing, for example, in audio and sonar systems. The AD641 ripple in the transfer function of ± 0.15 dB from the ideal re- is intended for use in demodulating applications. Each stage sponse when the input is either a dc voltage or a square wave. incorporates a detector (a full-wave transconductance rectifier) The slope of the transfer function is unaffected by the input whose output current depends on the absolute value of its input waveform; however, the intercept and ripple are waveform de- voltage. pendent (see EFFECT OF WAVEFORM ON INTERCEPT). Figure 16 is a simplified schematic of one stage of the AD641. The input will usually be an amplitude modulated sinusoidal All transistors in the basic cell operate at near zero collector to carrier. In these circumstances the output is a fluctuating cur- base voltage and low bias currents, resulting in low levels of rent at twice the carrier frequency (because of the full wave thermally induced distortion. These arise when power shifts detection) whose average value is extracted by an external low from one set of transistors to another during large input signals. pass filter, which recovers a logarithmic measure of the base- Rapid recovery is essential when a small signal immediately band signal. follows a large one. This low power operation also contributes
Circuit Operation
significantly to the excellent long term calibration stability of the With reference to Figure 16, the transconductance pair Q7, Q8 AD641. and load resistors R3 and R4 form a limiting amplifier having a The complete AD641, shown in Figure 17, includes two bias small signal gain of 10 dB, set by the tail current of nominally regulators. One determines the small signal gain of the ampli- 2.18 mA at 27°C. This current is basically proportional to abso- fier stages; the other determines the logarithmic slope. These lute temperature (PTAT) but includes additional current to bias regulators maintain a high degree of stability in the re- compensate for finite beta and junction resistance. The limiting sulting function by compensating for potentially large uncer- output voltage is ± 180 mV at +27°C and is PTAT. Emitter tainties in transistor parameters, temperature and supply followers Q1 and Q2 raise the input resistance of the stage, voltages. A third biasing block is used to accurately control provide level shifting to introduce collector bias for the gain the logarithmic intercept. stage and detectors, reduce offset drift by forming a thermally balanced quad with Q7 and Q8 and generate the detector bias- ing across resistors R1 and R2.
RG1 RG0 RG2 LOG OUT LOG COM 1k
V
1k
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COM 18 17 16 15 14 13 INTERCEPT POSITIONING BIAS 12 +VS FULL-WAVE FULL-WAVE FULL-WAVE FULL-WAVE FULL-WAVE DETECTOR DETECTOR DETECTOR DETECTOR DETECTOR ATN OUT 19 SIG +IN 20 11 SIG +OUT 10dB 10dB 10dB 10dB 10dB SIG –IN 1 10 SIG –OUT ATN LO 2 AMPLIFIER/LIMITER AMPLIFIER/LIMITER AMPLIFIER/LIMITER AMPLIFIER/LIMITER AMPLIFIER/LIMITER 27
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ATN COM 3 9 BL2 30
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270
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ATN COM 4 5 6 GAIN BIAS REGULATOR 7 SLOPE BIAS REGULATOR 8 ITC ATN IN BL1 –VS
Figure 17. Block Diagram of the Complete AD641 –6– REV. D Document Outline FEATURES PRODUCT DESCRIPTION PIN CONFIGURATIONS AD641--SPECIFICATIONS ELECTRICAL CHARACTERISTICS THERMAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION REVISION HISTORY AD641--TYPICAL DC PERFORMANCE CHARACTERISTICS TYPICAL AC PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION CIRCUIT OPERATION FUNDAMENTALS OF LOGARITHMIC CONVERSION INTERCEPT STABILIZATION CONVERSION RANGE EFFECT OF WAVEFORM ON INTERCEPT LOGARITHMIC CONFORMANCE AND WAVEFORM SIGNAL MAGNITUDE INTERCEPT AND LOGARITHMIC OFFSET OPERATION OF A SINGLE AD641 ACTIVE CURENT-TO-VOLTAGE CONVERSION EFFECT OF FREQUENCY ON CALIBRATION SOURCE RESISTANCE AND INPUT OFFSET USING HIGHER SUPPLY VOLTAGES USING THE ATTENUATOR OPERATION OF CASCADED AD641s ELIMINATING THE EFFECT OF FIRST STAGE OFFSET PRACTICAL APPLICATIONS RSSI APPLICATIONS 250 MHz RSSI CONVERTER WITH 58 dB DYNAMIC RANGE OUTLINE DIMENSIONS ORDERING GUIDE