Datasheet LTC6900 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Low Power, 1kHz to 20MHz Resistor Set SOT-23 Oscillator |
| Pages / Page | 12 / 6 — OPERATION. Figure 1. V+ – VSET Variation with IRES. Figure 2. RSET vs … |
| File Format / Size | PDF / 164 Kb |
| Document Language | English |
OPERATION. Figure 1. V+ – VSET Variation with IRES. Figure 2. RSET vs Desired Output Frequency
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LTC6900
OPERATION
As shown in the Block Diagram, the LTC6900’s master os- (Pin 5). The divide-by value is determined by the state of cillator is controlled by the ratio of the voltage between the the DIV input (Pin 4). Tie DIV to GND or drive it below 0.5V V+ and SET pins and the current (IRES) is entering the SET to select ÷1. This is the highest frequency range, with the pin. The voltage on the SET pin is forced to approximately master output frequency passed directly to OUT. The DIV 1.1V below V+ by the PMOS transistor and its gate bias pin may be fl oated or driven to midsupply to select ÷10, voltage. This voltage is accurate to ± 8% at a particular the intermediate frequency range. The lowest frequency input current and supply voltage (see Figure 1). range, ÷100, is selected by tying DIV to V+ or driving it to within 0.4V of V+. Figure 2 shows the relationship between A resistor RSET, connected between the V+ and SET pins, R “locks together” the voltage (V+ – V SET, divider setting and output frequency, including the SET) and current, IRES, overlapping frequency ranges near 100kHz and 1MHz. variation. This provides the LTC6900’s high precision. The master oscillation frequency reduces to: The CMOS output driver has an on resistance that is typi- ⎛ ⎞ cally less than 100Ω. In the ÷1 (high frequency) mode, ƒ 20kΩ the rise and fall times are typically 7ns with a 5V supply MO = 10MHz • ⎝⎜ R ⎠⎟ SET and 11ns with a 3V supply. These times maintain a clean square wave at 10MHz (20MHz at 5V supply). In the ÷10 The LTC6900 is optimized for use with resistors between and ÷100 modes, where the output frequency is much lower, 10k and 2M, corresponding to master oscillator frequen- slew rate control circuitry in the output driver increases cies between 100kHz and 20MHz. the rise/fall times to typically 14ns for a 5V supply and To extend the output frequency range, the master oscillator 19ns for a 3V supply. The reduced slew rate lowers EMI signal may be divided by 1, 10 or 100 before driving OUT (electromagnetic interference) and supply bounce. 1.4 10000 1.3 1000 V+ = 5V ÷100 ÷10 ÷1 1.2 SET – V V+ = 3V + 1.1 (kΩ) 100 = V SETR RESV 1.0 10 0.9 0.8 1 0.1 1 10 100 1000 1k 10k 100k 1M 10M 100M IRES (μA) DESIRED OUTPUT FREQUENCY (Hz) 6900 F02 6900 F01
Figure 1. V+ – VSET Variation with IRES Figure 2. RSET vs Desired Output Frequency
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OPERATION
As shown in the Block Diagram, the LTC6900’s master os- (Pin 5). The divide-by value is determined by the state of cillator is controlled by the ratio of the voltage between the the DIV input (Pin 4). Tie DIV to GND or drive it below 0.5V V+ and SET pins and the current (IRES) is entering the SET to select ÷1. This is the highest frequency range, with the pin. The voltage on the SET pin is forced to approximately master output frequency passed directly to OUT. The DIV 1.1V below V+ by the PMOS transistor and its gate bias pin may be fl oated or driven to midsupply to select ÷10, voltage. This voltage is accurate to ± 8% at a particular the intermediate frequency range. The lowest frequency input current and supply voltage (see Figure 1). range, ÷100, is selected by tying DIV to V+ or driving it to within 0.4V of V+. Figure 2 shows the relationship between A resistor RSET, connected between the V+ and SET pins, R “locks together” the voltage (V+ – V SET, divider setting and output frequency, including the SET) and current, IRES, overlapping frequency ranges near 100kHz and 1MHz. variation. This provides the LTC6900’s high precision. The master oscillation frequency reduces to: The CMOS output driver has an on resistance that is typi- ⎛ ⎞ cally less than 100Ω. In the ÷1 (high frequency) mode, ƒ 20kΩ the rise and fall times are typically 7ns with a 5V supply MO = 10MHz • ⎝⎜ R ⎠⎟ SET and 11ns with a 3V supply. These times maintain a clean square wave at 10MHz (20MHz at 5V supply). In the ÷10 The LTC6900 is optimized for use with resistors between and ÷100 modes, where the output frequency is much lower, 10k and 2M, corresponding to master oscillator frequen- slew rate control circuitry in the output driver increases cies between 100kHz and 20MHz. the rise/fall times to typically 14ns for a 5V supply and To extend the output frequency range, the master oscillator 19ns for a 3V supply. The reduced slew rate lowers EMI signal may be divided by 1, 10 or 100 before driving OUT (electromagnetic interference) and supply bounce. 1.4 10000 1.3 1000 V+ = 5V ÷100 ÷10 ÷1 1.2 SET – V V+ = 3V + 1.1 (kΩ) 100 = V SETR RESV 1.0 10 0.9 0.8 1 0.1 1 10 100 1000 1k 10k 100k 1M 10M 100M IRES (μA) DESIRED OUTPUT FREQUENCY (Hz) 6900 F02 6900 F01
Figure 1. V+ – VSET Variation with IRES Figure 2. RSET vs Desired Output Frequency
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