Datasheet LTC6907 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Micropower, 40kHz to 4MHz Resistor Set Oscillator in SOT-23 |
| Pages / Page | 12 / 5 — PI FU CTIO S. OUT (Pin 1):. GND (Pin 2):. GRD (Pin 5):. DIV (Pin 3):. SET … |
| File Format / Size | PDF / 175 Kb |
| Document Language | English |
PI FU CTIO S. OUT (Pin 1):. GND (Pin 2):. GRD (Pin 5):. DIV (Pin 3):. SET (Pin 4):. V+ (Pin 6):. BLOCK DIAGRA
Model Line for this Datasheet
Text Version of Document
LTC6907
U U U PI FU CTIO S OUT (Pin 1):
Oscillator Output. The OUT pin swings from or better temperature coefficient. For lower accuracy GND to V+ with an output resistance of approximately applications, an inexpensive 1% thick-film resistor may be 150Ω. For micropower operation, the load resistance used. Limit the capacitance in parallel with RSET to less must be kept as high as possible and the load capacitance than 10pF to reduce jitter and to ensure stability. The as low as possible. voltage on the SET pin is approximately 650mV at 25°C and decreases with temperature by about –2.3mV/°C.
GND (Pin 2):
Ground.
GRD (Pin 5):
Guard Signal. This pin can be used to reduce
DIV (Pin 3):
Divider Setting Input. This three-level input PC board leakage across the frequency setting resistor, selects one of three internal digital divider settings, deter- R mining the value of N in the frequency equation. Tie to GND SET. The GRD pin is held within a few millivolts of the SET pin and shunts leakage current away from the SET pin. To for ÷1, leave floating for ÷3 and tie to V+ for ÷10. When left control leakage, connect a bare copper trace (a trace with floating, the LTC6907 pulls Pin 3 to mid-supply with a no solder mask) to GRD and loop it around the SET pin and 2.5M resistor. When Pin 3 is floating, care should be taken all PC board metal connected to SET. Careful attention to to reduce coupling from the OUT pin and its trace to Pin 3. board layout and assembly can prevent leakage currents. Coupling can be reduced by increasing the physical space The use of a guard ring provides additional shielding of between traces or by shielding the DIV pin with grounded leakage currents from the SET pin and is optional. If metal. unused, the GRD pin should be left unconnected.
SET (Pin 4):
Frequency Setting Resistor Input. Connect a
V+ (Pin 6):
Voltage Supply (3V to 3.6V). A 0.1µF resistor, RSET, from this pin to GND to set the oscillator decoupling capacitor should be placed as close as pos- frequency. For best performance use a precision metal or sible to this pin for best performance. thin-film resistor of 0.1% or better tolerance and 50ppm/°C
W BLOCK DIAGRA
V+ FREQUENCY-TO-CURRENT CONVERTERS V+ 5M 6 fOSC THREE-LEVEL DIV INPUT 3 GND 2 I I FB FB DETECTOR 5M DIVIDER VSET ≅ VGRD ≅ 650mV SELECT ISET = IFB VSET SET VSET – f 150Ω DRIVER 4 OSC VOLTAGE PROGRAMMABLE CONTROLLED OUT OP AMP DIVIDER (n) 1 RSET BUFFER + OSCILLATOR (÷1, ÷3, ÷10) (MASTER OSCILLATOR) GRD VSET 5 50kΩ fOSC = 4MHz • RSET 6907 BD 6907fa 5
U U U PI FU CTIO S OUT (Pin 1):
Oscillator Output. The OUT pin swings from or better temperature coefficient. For lower accuracy GND to V+ with an output resistance of approximately applications, an inexpensive 1% thick-film resistor may be 150Ω. For micropower operation, the load resistance used. Limit the capacitance in parallel with RSET to less must be kept as high as possible and the load capacitance than 10pF to reduce jitter and to ensure stability. The as low as possible. voltage on the SET pin is approximately 650mV at 25°C and decreases with temperature by about –2.3mV/°C.
GND (Pin 2):
Ground.
GRD (Pin 5):
Guard Signal. This pin can be used to reduce
DIV (Pin 3):
Divider Setting Input. This three-level input PC board leakage across the frequency setting resistor, selects one of three internal digital divider settings, deter- R mining the value of N in the frequency equation. Tie to GND SET. The GRD pin is held within a few millivolts of the SET pin and shunts leakage current away from the SET pin. To for ÷1, leave floating for ÷3 and tie to V+ for ÷10. When left control leakage, connect a bare copper trace (a trace with floating, the LTC6907 pulls Pin 3 to mid-supply with a no solder mask) to GRD and loop it around the SET pin and 2.5M resistor. When Pin 3 is floating, care should be taken all PC board metal connected to SET. Careful attention to to reduce coupling from the OUT pin and its trace to Pin 3. board layout and assembly can prevent leakage currents. Coupling can be reduced by increasing the physical space The use of a guard ring provides additional shielding of between traces or by shielding the DIV pin with grounded leakage currents from the SET pin and is optional. If metal. unused, the GRD pin should be left unconnected.
SET (Pin 4):
Frequency Setting Resistor Input. Connect a
V+ (Pin 6):
Voltage Supply (3V to 3.6V). A 0.1µF resistor, RSET, from this pin to GND to set the oscillator decoupling capacitor should be placed as close as pos- frequency. For best performance use a precision metal or sible to this pin for best performance. thin-film resistor of 0.1% or better tolerance and 50ppm/°C
W BLOCK DIAGRA
V+ FREQUENCY-TO-CURRENT CONVERTERS V+ 5M 6 fOSC THREE-LEVEL DIV INPUT 3 GND 2 I I FB FB DETECTOR 5M DIVIDER VSET ≅ VGRD ≅ 650mV SELECT ISET = IFB VSET SET VSET – f 150Ω DRIVER 4 OSC VOLTAGE PROGRAMMABLE CONTROLLED OUT OP AMP DIVIDER (n) 1 RSET BUFFER + OSCILLATOR (÷1, ÷3, ÷10) (MASTER OSCILLATOR) GRD VSET 5 50kΩ fOSC = 4MHz • RSET 6907 BD 6907fa 5
