Datasheet LTC2323-16 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Dual, 16-Bit, 5Msps Differential Input ADC with Wide Input Common Mode Range |
| Pages / Page | 26 / 8 — PIN FUNCTIONS. VDD (Pins 1, 8):. SDO1+, SDO1– (Pins 15, 16):. IN2+, AIN2– … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
PIN FUNCTIONS. VDD (Pins 1, 8):. SDO1+, SDO1– (Pins 15, 16):. IN2+, AIN2– (Pins 2, 3):. GND (Pins 4, 5, 10, 29):
Model Line for this Datasheet
Text Version of Document
LTC2323-16
PIN FUNCTIONS VDD (Pins 1, 8):
Power Supply. Bypass VDD to GND with
SDO1+, SDO1– (Pins 15, 16):
Channel 1 Serial Data a 10µF ceramic and a 0.1µF ceramic close to the part. The Output. The conversion result is shifted MSB first on each VDD pins should be shorted together and driven from the falling edge of SCK. In CMOS mode, the result is output same supply. on SDO1+. The logic level is determined by OVDD. Do
A
not connect SDO1–. In LVDS mode, the result is output
IN2+, AIN2– (Pins 2, 3):
Analog Differential Input Pins. Full-scale range (A differentially on SDO1+ and SDO1–. These pins must be IN2+ – AIN2–) is ±REFOUT2 voltage. These pins can be driven from V differentially terminated by an external 100Ω resistor at DD to GND. the receiver (FPGA).
GND (Pins 4, 5, 10, 29):
Ground. These pins and exposed pad (Pin 29) must be tied directly to a solid ground plane.
CLKOUT+, CLKOUT– (Pins 17, 18):
Serial Data Clock Output. CLKOUT provides a skew-matched clock to latch
AIN1–, AIN1+ (Pins 6, 7):
Analog Differential Input Pins. the SDO output at the receiver. In CMOS mode, the skew- Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage. matched clock is output on CLKOUT+. The logic level is These pins can be driven from VDD to GND. determined by OVDD. Do not connect CLKOUT–. For low
CNV (Pin 9):
Conversion Start Input. A falling edge on CNV throughput applications using SCK to latch the SDO out- puts the internal sample-and-hold into the hold mode and put, CLKOUT+ can be disabled by tying CLKOUT– to OVDD. starts a conversion cycle. CNV must be driven by a low In LVDS mode, the skew-matched clock is output differ- jitter clock as shown in the application circuit on page 26. entially on CLKOUT+ and CLKOUT–. These pins must be The CNV pin is unaffected by the CMOS/LVDS pin
.
differentially terminated by an external 100Ω resistor at the receiver (FPGA).
REFRTN1 (Pin 11):
Reference Buffer 1 Output Return. Bypass REFRTN1 to REFOUT1. Do not tie the REFRTN1
SDO2+, SDO2– (Pins 19, 20):
Channel 2 Serial Data pin to the ground plane. Output. The conversion result is shifted MSB first on each falling edge of SCK. In CMOS mode, the result is output
REFOUT1 (Pin 12):
Reference Buffer 1 Output. An onboard on SDO2+. The logic level is determined by OV buffer nominally outputs 4.096V to this pin. This pin is DD. Do not connect SDO2–. In LVDS mode, the result is output referred to REFRTN1 and should be decoupled closely to differentially on SDO2+ and SDO2–. These pins must be the pin (no vias) with a 0.1µF (X7R, 0402 size) capacitor differentially terminated by an external 100Ω resistor at and a 10μF (X5R, 0805 size) ceramic capacitor in paral- the receiver (FPGA). lel. The internal buffer driving this pin may be disabled by grounding the REFINT pin. If the buffer is disabled,
SCK+, SCK– (Pins 21, 22):
Serial Data Clock Input. The an external reference may drive this pin in the range of falling edge of this clock shifts the conversion result MSB 1.25V to 5V. first onto the SDO pins. In CMOS mode, drive SCK+ with a single-ended clock. The logic level is determined by
VBYP1 (Pin 13):
Bypass this internally supplied pin to OV ground with a 1µF ceramic capacitor. The nominal output DD. Do not connect SCK–. In LVDS mode, drive SCK+ and SCK– with a differential clock. These pins must be voltage on this pin is 1.6V. differentially terminated by an external 100Ω resistor at
OVDD (Pin 14):
I/O Interface Digital Power. The range of the receiver (ADC). OVDD is 1.71V to 2.5V. This supply is nominally set to
OGND (Pin 23):
I/O Ground. This ground must be tied to the same supply as the host interface (CMOS: 1.8V or the ground plane at a single point. OV 2.5V, LVDS: 2.5V). Bypass OV DD is bypassed to DD to OGND with a 0.1μF this pin. capacitor. 232316fc 8 For more information www.linear.com/LTC2323-16 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts
PIN FUNCTIONS VDD (Pins 1, 8):
Power Supply. Bypass VDD to GND with
SDO1+, SDO1– (Pins 15, 16):
Channel 1 Serial Data a 10µF ceramic and a 0.1µF ceramic close to the part. The Output. The conversion result is shifted MSB first on each VDD pins should be shorted together and driven from the falling edge of SCK. In CMOS mode, the result is output same supply. on SDO1+. The logic level is determined by OVDD. Do
A
not connect SDO1–. In LVDS mode, the result is output
IN2+, AIN2– (Pins 2, 3):
Analog Differential Input Pins. Full-scale range (A differentially on SDO1+ and SDO1–. These pins must be IN2+ – AIN2–) is ±REFOUT2 voltage. These pins can be driven from V differentially terminated by an external 100Ω resistor at DD to GND. the receiver (FPGA).
GND (Pins 4, 5, 10, 29):
Ground. These pins and exposed pad (Pin 29) must be tied directly to a solid ground plane.
CLKOUT+, CLKOUT– (Pins 17, 18):
Serial Data Clock Output. CLKOUT provides a skew-matched clock to latch
AIN1–, AIN1+ (Pins 6, 7):
Analog Differential Input Pins. the SDO output at the receiver. In CMOS mode, the skew- Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage. matched clock is output on CLKOUT+. The logic level is These pins can be driven from VDD to GND. determined by OVDD. Do not connect CLKOUT–. For low
CNV (Pin 9):
Conversion Start Input. A falling edge on CNV throughput applications using SCK to latch the SDO out- puts the internal sample-and-hold into the hold mode and put, CLKOUT+ can be disabled by tying CLKOUT– to OVDD. starts a conversion cycle. CNV must be driven by a low In LVDS mode, the skew-matched clock is output differ- jitter clock as shown in the application circuit on page 26. entially on CLKOUT+ and CLKOUT–. These pins must be The CNV pin is unaffected by the CMOS/LVDS pin
.
differentially terminated by an external 100Ω resistor at the receiver (FPGA).
REFRTN1 (Pin 11):
Reference Buffer 1 Output Return. Bypass REFRTN1 to REFOUT1. Do not tie the REFRTN1
SDO2+, SDO2– (Pins 19, 20):
Channel 2 Serial Data pin to the ground plane. Output. The conversion result is shifted MSB first on each falling edge of SCK. In CMOS mode, the result is output
REFOUT1 (Pin 12):
Reference Buffer 1 Output. An onboard on SDO2+. The logic level is determined by OV buffer nominally outputs 4.096V to this pin. This pin is DD. Do not connect SDO2–. In LVDS mode, the result is output referred to REFRTN1 and should be decoupled closely to differentially on SDO2+ and SDO2–. These pins must be the pin (no vias) with a 0.1µF (X7R, 0402 size) capacitor differentially terminated by an external 100Ω resistor at and a 10μF (X5R, 0805 size) ceramic capacitor in paral- the receiver (FPGA). lel. The internal buffer driving this pin may be disabled by grounding the REFINT pin. If the buffer is disabled,
SCK+, SCK– (Pins 21, 22):
Serial Data Clock Input. The an external reference may drive this pin in the range of falling edge of this clock shifts the conversion result MSB 1.25V to 5V. first onto the SDO pins. In CMOS mode, drive SCK+ with a single-ended clock. The logic level is determined by
VBYP1 (Pin 13):
Bypass this internally supplied pin to OV ground with a 1µF ceramic capacitor. The nominal output DD. Do not connect SCK–. In LVDS mode, drive SCK+ and SCK– with a differential clock. These pins must be voltage on this pin is 1.6V. differentially terminated by an external 100Ω resistor at
OVDD (Pin 14):
I/O Interface Digital Power. The range of the receiver (ADC). OVDD is 1.71V to 2.5V. This supply is nominally set to
OGND (Pin 23):
I/O Ground. This ground must be tied to the same supply as the host interface (CMOS: 1.8V or the ground plane at a single point. OV 2.5V, LVDS: 2.5V). Bypass OV DD is bypassed to DD to OGND with a 0.1μF this pin. capacitor. 232316fc 8 For more information www.linear.com/LTC2323-16 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Related Parts
