Datasheet MCP6031, MCP6032, MCP6035, MCP6034 (Microchip) - 6
| Manufacturer | Microchip |
| Description | The MCP6031 operational amplifier (op amp) has a gain bandwidth of 10 kHz with a low typical operating current of 900 nA and an offset voltage that is less than 150 uV |
| Pages / Page | 34 / 6 — MCP6031/2/3/4. 2.0. TYPICAL PERFORMANCE CURVES. Note:. 14%. 400. 640 … |
| File Format / Size | PDF / 652 Kb |
| Document Language | English |
MCP6031/2/3/4. 2.0. TYPICAL PERFORMANCE CURVES. Note:. 14%. 400. 640 Samples. V) 300. TA = -40°C. 12%. VDD = 3.0V. TA = +25°C. 200. CM = VDD/3. 10%
Model Line for this Datasheet
- MCP6031-E/MC MCP6031-E/MS MCP6031-E/P MCP6031-E/SN MCP6031T-E/MC MCP6031T-E/MS MCP6031T-E/OT MCP6031T-E/OTVAO MCP6031T-E/SN
Text Version of Document
MCP6031/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 MΩ to VL , CL = 60 pF and CS is tied low.
14% 400 640 Samples V) 300 TA = -40°C 12% VDD = 3.0V μ TA = +25°C V 200 CM = VDD/3 T 10% A = +85°C age ( lt 100 TA = +125°C Occurences 8% o V 0 6% fset -100 4% -200 2% -300 Input Of V Percentage of DD = 5.5V 0% -400 .5 0 5 0 5 0 5 0 5 0 5 0 5 0 -150 -120 -90 -60 -30 0 30 60 90 120 150 -0 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. Input Offset Voltage (μV) Common Mode Input Voltage (V) FIGURE 2-1:
Input Offset Voltage with
FIGURE 2-4:
Input Offset Voltage vs. VDD = 3.0V. Common Mode Input Voltage with VDD = 5.5V.
22% 400 T 20% A = -40°C 640 Samples V) 300 T 18% V A = +25°C DD = 3.0V μ T rences A = +85°C 16% V e ( 200 CM = VDD/3 TA = +125°C 14% T ccu A = -40°C to +85°C tag 100 O 12% Vol 0 10% e of 8% -100 ffset 6% t O -200 4% pu -300 2% In Percentag VDD = 1.8V 0% -400 .4 .2 0 2 4 6 8 0 2 4 6 8 0 2 -20 -16 -12 -8 -4 0 4 8 12 16 20 -0 -0 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 2. Input Offset Drift with Temperature (μV/°C) Common Mode Input Voltage (V) FIGURE 2-2:
Input Offset Voltage Drift
FIGURE 2-5:
Input Offset Voltage vs. with VDD = 3.0V and TA ≤ +85°C. Common Mode Input Voltage with VDD = 1.8V.
14% 250 640 Samples 12% 200 V V) DD = 3.0V V 150 10% CM = VDD/3 e (μ T 100 A = +85°C to +125°C VDD = 3.0V VDD = 5.5V 8% ltag 50 0 6% t Vo -50 age of Occurences 4% ffse -100 VDD = 1.8V 2% -150 Percent -200 Input O 0% -250 -30 -24 -18 -12 -6 0 6 12 18 24 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Offset Drift with Temperature (μV/°C) Output Voltage (V) FIGURE 2-3:
Input Offset Voltage Drift
FIGURE 2-6:
Input Offset Voltage vs. with VDD = 3.0V and TA ≥ +85°C. Output Voltage. DS22041B-page 6 © 2008 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the CS Pin on the MCP6033. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage with VDD = 3.0V. FIGURE 2-2: Input Offset Voltage Drift with VDD = 3.0V and TA £ +85˚C. FIGURE 2-3: Input Offset Voltage Drift with VDD = 3.0V and TA ³ +85˚C. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.8V. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-9: Common Mode Rejection Ratio, Power Supply Rejection Ratio vs. Frequency. FIGURE 2-10: Common Mode Rejection Ratio, Power Supply Rejection Ratio vs. Ambient Temperature. FIGURE 2-11: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-12: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-13: Quiescent Current vs Ambient Temperature. FIGURE 2-14: Quiescent Current vs. Power Supply Voltage with VCM = VDD. FIGURE 2-15: Quiescent Current vs. Power Supply Voltage with VCM = VSS. FIGURE 2-16: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel-to-Channel Separation vs. Frequency ( MCP6032/4 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-23: Ouput Short Circuit Current vs. Power Supply Voltage. FIGURE 2-24: Output Voltage Swing vs. Frequency. FIGURE 2-25: Output Voltage Headroom vs. Output Current. FIGURE 2-26: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-27: Slew Rate vs. Ambient Temperature. FIGURE 2-28: Small Signal Non-Inverting Pulse Response. FIGURE 2-29: Small Signal Inverting Pulse Response. FIGURE 2-30: Large Signal Non-Inverting Pulse Response. FIGURE 2-31: Large Signal Inverting Pulse Response. FIGURE 2-32: The MCP6031/2/3/4 family shows no phase reversal . FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time (MCP6033 only). FIGURE 2-34: Chip Select (CS) Hysteresis (MCP6033 only) with VDD = 5.5V. FIGURE 2-35: Chip Select (CS) Hysteresis (MCP6033 only) with VDD = 3.0V. FIGURE 2-36: Chip Select (CS) Hysteresis (MCP6033 only) with VDD = 1.8V. FIGURE 2-37: Closed Loop Output Impedance vs. Frequency. FIGURE 2-38: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Application Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Capacitive Loads FIGURE 4-3: Output resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO values for Capacitive Loads. 4.5 MCP6033 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-7: High Side Battery Current Sensor. FIGURE 4-8: Precision, Non-inverting Comparator. FIGURE 4-9: Driving the MCP3421 using an R-C Snubber. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 MΩ to VL , CL = 60 pF and CS is tied low.
14% 400 640 Samples V) 300 TA = -40°C 12% VDD = 3.0V μ TA = +25°C V 200 CM = VDD/3 T 10% A = +85°C age ( lt 100 TA = +125°C Occurences 8% o V 0 6% fset -100 4% -200 2% -300 Input Of V Percentage of DD = 5.5V 0% -400 .5 0 5 0 5 0 5 0 5 0 5 0 5 0 -150 -120 -90 -60 -30 0 30 60 90 120 150 -0 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. Input Offset Voltage (μV) Common Mode Input Voltage (V) FIGURE 2-1:
Input Offset Voltage with
FIGURE 2-4:
Input Offset Voltage vs. VDD = 3.0V. Common Mode Input Voltage with VDD = 5.5V.
22% 400 T 20% A = -40°C 640 Samples V) 300 T 18% V A = +25°C DD = 3.0V μ T rences A = +85°C 16% V e ( 200 CM = VDD/3 TA = +125°C 14% T ccu A = -40°C to +85°C tag 100 O 12% Vol 0 10% e of 8% -100 ffset 6% t O -200 4% pu -300 2% In Percentag VDD = 1.8V 0% -400 .4 .2 0 2 4 6 8 0 2 4 6 8 0 2 -20 -16 -12 -8 -4 0 4 8 12 16 20 -0 -0 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 2. Input Offset Drift with Temperature (μV/°C) Common Mode Input Voltage (V) FIGURE 2-2:
Input Offset Voltage Drift
FIGURE 2-5:
Input Offset Voltage vs. with VDD = 3.0V and TA ≤ +85°C. Common Mode Input Voltage with VDD = 1.8V.
14% 250 640 Samples 12% 200 V V) DD = 3.0V V 150 10% CM = VDD/3 e (μ T 100 A = +85°C to +125°C VDD = 3.0V VDD = 5.5V 8% ltag 50 0 6% t Vo -50 age of Occurences 4% ffse -100 VDD = 1.8V 2% -150 Percent -200 Input O 0% -250 -30 -24 -18 -12 -6 0 6 12 18 24 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Offset Drift with Temperature (μV/°C) Output Voltage (V) FIGURE 2-3:
Input Offset Voltage Drift
FIGURE 2-6:
Input Offset Voltage vs. with VDD = 3.0V and TA ≥ +85°C. Output Voltage. DS22041B-page 6 © 2008 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the CS Pin on the MCP6033. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage with VDD = 3.0V. FIGURE 2-2: Input Offset Voltage Drift with VDD = 3.0V and TA £ +85˚C. FIGURE 2-3: Input Offset Voltage Drift with VDD = 3.0V and TA ³ +85˚C. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.8V. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-9: Common Mode Rejection Ratio, Power Supply Rejection Ratio vs. Frequency. FIGURE 2-10: Common Mode Rejection Ratio, Power Supply Rejection Ratio vs. Ambient Temperature. FIGURE 2-11: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-12: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-13: Quiescent Current vs Ambient Temperature. FIGURE 2-14: Quiescent Current vs. Power Supply Voltage with VCM = VDD. FIGURE 2-15: Quiescent Current vs. Power Supply Voltage with VCM = VSS. FIGURE 2-16: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel-to-Channel Separation vs. Frequency ( MCP6032/4 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-23: Ouput Short Circuit Current vs. Power Supply Voltage. FIGURE 2-24: Output Voltage Swing vs. Frequency. FIGURE 2-25: Output Voltage Headroom vs. Output Current. FIGURE 2-26: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-27: Slew Rate vs. Ambient Temperature. FIGURE 2-28: Small Signal Non-Inverting Pulse Response. FIGURE 2-29: Small Signal Inverting Pulse Response. FIGURE 2-30: Large Signal Non-Inverting Pulse Response. FIGURE 2-31: Large Signal Inverting Pulse Response. FIGURE 2-32: The MCP6031/2/3/4 family shows no phase reversal . FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time (MCP6033 only). FIGURE 2-34: Chip Select (CS) Hysteresis (MCP6033 only) with VDD = 5.5V. FIGURE 2-35: Chip Select (CS) Hysteresis (MCP6033 only) with VDD = 3.0V. FIGURE 2-36: Chip Select (CS) Hysteresis (MCP6033 only) with VDD = 1.8V. FIGURE 2-37: Closed Loop Output Impedance vs. Frequency. FIGURE 2-38: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Application Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Capacitive Loads FIGURE 4-3: Output resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO values for Capacitive Loads. 4.5 MCP6033 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-7: High Side Battery Current Sensor. FIGURE 4-8: Precision, Non-inverting Comparator. FIGURE 4-9: Driving the MCP3421 using an R-C Snubber. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information
