Datasheet MCP616, MCP617, MCP618, MCP619 (Microchip) - 7

MCP616/7/8/9 2.0 TYPICAL PERFORMANCE CURVES Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF.
20% s 14% 598 Samples ce 598 Samples 18% ces 12% V V DD = 5.5V DD = 5.5V 16% rren rren TA = -40°C to +85°C u 10% 14% c c 8% 12% f O f Occu 10% o 6% o e e 8% g g 4% ta ta 6% en 2% 4% rc e 2% P 0% Percen 0 0 0 0 0 0% -8 -6 -4 -2 20 40 60 80 0 -8 -6 -4 -2 0 2 4 6 8 -100 100 -1 10 Input Offset Voltage (µV) Input Offset Voltage Drift (µV/°C) FIGURE 2-1:
Input Offset Voltage at
FIGURE 2-4:
Input Offset Voltage Drift at VDD = 5.5V. VDD = 5.5V.
16% 18% 598 Samples 598 Samples ces 16% 14% V V ces DD = 2.3V DD = 2.3V 14% T rren 12% A = -40°C to +85°C rren 12% 10% 10% f Occu 8% f Occu o e o 8% 6% g e g ta 6% 4% ta 4% 2% Percen 2% 0% Percen 0 0 0 0 0 0% -6 -4 -2 20 40 60 80 0 -100 -8 100 -8 -6 -4 -2 0 2 4 6 8 -1 10 Offset Voltage (µV) Input Offset Voltage Drift (µV/°C) FIGURE 2-2:
Input Offset Voltage at
FIGURE 2-5:
Input Offset Voltage Drift at VDD = 2.3V. VDD = 2.3V.
16% 20% 600 Samples ces 14% 600 Samples ces 18% n VDD = 5.5V V 16% DD = 5.5V rre 12% rren 14% ccu 10% 12% f O 8% f Occu 10% o o e 6% e 8% g g ta ta 6% 4% 4% cen 2% 2% Per Percen 0% 0% 2 1 0 9 8 7 6 5 4 3 2 1 0 .7 .6 .5 .4 .3 .2 .1 -2 -2 -2 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -0 -0 -0 -0 -0 -0 -0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Input Bias Current (nA) Input Offset Current (nA) FIGURE 2-3:
Input Bias Current at
FIGURE 2-6:
Input Offset Current at VDD = 5.5V. VDD = 5.5V. © 2008 Microchip Technology Inc. DS21613C-page 7 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the CS Pin on the MCP618. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage at VDD = 5.5V. FIGURE 2-2: Input Offset Voltage at VDD = 2.3V. FIGURE 2-3: Input Bias Current at VDD = 5.5V. FIGURE 2-4: Input Offset Voltage Drift at VDD = 5.5V. FIGURE 2-5: Input Offset Voltage Drift at VDD = 2.3V. FIGURE 2-6: Input Offset Current at VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Ambient Temperature. FIGURE 2-8: Quiescent Current vs. Ambient Temperature. FIGURE 2-9: Maximum Output Voltage Swing vs. Ambient Temperature at RL = 5 kW. FIGURE 2-10: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-12: Maximum Output Voltage Swing vs. Ambient Temperature at RL = 25 kW. FIGURE 2-13: Output Short Circuit Current vs. Ambient Temperature. FIGURE 2-14: Slew Rate vs. Ambient Temperature. FIGURE 2-15: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-16: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-17: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-18: Input Offset Voltage vs. Output Voltage. FIGURE 2-19: Quiescent Current vs. Power Supply Voltage. FIGURE 2-20: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-21: Gain-Bandwidth Product, Phase Margin vs. Load Resistance. FIGURE 2-22: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-23: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP617 and MCP619 only). FIGURE 2-25: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-26: Input Noise Voltage, Current Densities vs. Frequency. FIGURE 2-27: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-28: CMRR, PSRR vs. Frequency. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small-Signal, Inverting Pulse Response. FIGURE 2-31: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP618 only). FIGURE 2-33: The MCP616/7/8/9 Show No Phase Reversal. FIGURE 2-34: Large-Signal, Inverting Pulse Response. FIGURE 2-35: Chip Select (CS) Internal Hysteresis (MCP618 only). FIGURE 2-36: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input (CS) 3.4 Power Supply Pins (VDD, VSS) 4.0 Applications Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 DC Offsets FIGURE 4-3: Example Circuit for Calculating DC Offset. FIGURE 4-4: Equivalent DC Circuit. 4.3 Rail-to-Rail Output 4.4 Capacitive Loads FIGURE 4-5: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-6: Recommended RISO Values for Capacitive Loads. 4.5 MCP618 Chip Select (CS) 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-7: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-8: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-9: High Gain Pre-amplifier. FIGURE 4-10: Two-Op Amp Instrumentation Amplifier. FIGURE 4-11: Three-Op Amp Instrumentation Amplifier. FIGURE 4-12: Precision Gain with Good Load Isolation. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 Mindi™ Circuit Designer & Simulator 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information