Datasheet MCP6V61, MCP6V61U, MCP6V62, MCP6V64 (Microchip) - 5

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MCP6V61/1U/2/4 TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics:
Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF (refer to Figures 1-4 and 1-5).
Parameters Sym. Min. Typ. Max. Units Conditions Amplifier AC Response
Gain Bandwidth Product GBWP — 1 — MHz Slew Rate SR — 0.45 — V/µs Phase Margin PM — 60 — °C G = +1
Amplifier Noise Response
Input Noise Voltage Eni — 0.17 — µVP-P f = 0.01 Hz to 1 Hz Eni — 0.54 — µVP-P f = 0.1 Hz to 10 Hz Input Noise Voltage Density eni — 26 — nV/√Hz f < 2 kHz Input Noise Current Density ini — 5 — fA/√Hz
Amplifier Distortion (Note 1 )
Intermodulation Distortion (AC) IMD — 48 — µVPK VCM tone = 50 mVPK at 1 kHz, GN = 11, RTI
Amplifier Step Response
Start-Up Time tSTR — 250 — µs G = +1, 0.1% VOUT settling
(Note 2 )
Offset Correction Settling Time tSTL — 30 — µs G = +1, VIN step of 2V, VOS within 100 µV of its final value Output Overdrive Recovery Time tODR — 60 — µs G = -10, ±0.5V input overdrive to VDD/2, VIN 50% point to VOUT 90% point
(Note 3) EMI Protection
EMI Rejection Ratio EMIRR — 80 — dB VIN = 0.1 VPK, f = 400 MHz — 96 — VIN = 0.1 VPK, f = 900 MHz — 101 — VIN = 0.1 VPK, f = 1800 MHz — 102 — VIN = 0.1 VPK, f = 2400 MHz
Note 1:
These parameters were characterized using the circuit in Figure 1-6. In Figures 2-40 and 2-41, there is an IMD tone at DC, a residual tone at 1 kHz and other IMD tones and clock tones. IMD is Referred to Input (RTI).
2:
High gains behave differently; see
Section 4.3.3 “Offset at Power-Up”
.
3:
tSTL and tODR include some uncertainty due to clock edge timing.
TABLE 1-3: TEMPERATURE SPECIFICATIONS Electrical Characteristics:
Unless otherwise indicated, all limits are specified for: VDD = +1.8V to +5.5V, VSS = GND
Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges
Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C
Note 1
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5LD-SC70 JA — 209 — °C/W Thermal Resistance, 5LD-SOT-23 JA — 201 — °C/W Thermal Resistance, 8L-2x3 TDFN JA — 53 — °C/W Thermal Resistance, 8L-MSOP JA — 211 — °C/W Thermal Resistance, 14L-TSSOP JA — 100 — °C/W
Note 1:
Operation must not cause TJ to exceed the Maximum Junction Temperature specification (+150°C).  2014-2015 Microchip Technology Inc. DS20005367B-page 5 Document Outline Features Typical Applications Design Aids Related Parts General Description Package Types Typical Application Circuit FIGURE 1: Input Offset Voltage vs. Ambient Temperature with VDD = 1.8V. FIGURE 2: Input Offset Voltage vs. Ambient Temperature with VDD = 5.5V. 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC Electrical Specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: Temperature Specifications 1.3 Timing Diagrams FIGURE 1-1: Amplifier Start-Up. FIGURE 1-2: Offset Correction Settling Time. FIGURE 1-3: Output Overdrive Recovery. 1.4 Test Circuits FIGURE 1-4: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-5: AC and DC Test Circuit for Most Inverting Gain Conditions. FIGURE 1-6: Test Circuit for Dynamic Input Behavior. 2.0 Typical Performance Curves 2.1 DC Input Precision FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage Quadratic Temp. Co. FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with VCM = VCML. FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMH. FIGURE 2-6: Input Offset Voltage vs. Output Voltage with VDD = 1.8V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage with VDD = 5.5V. FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 1.8V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V. FIGURE 2-10: Common Mode Rejection Ratio. FIGURE 2-11: Power Supply Rejection Ratio. FIGURE 2-12: DC Open-Loop Gain. FIGURE 2-13: CMRR and PSRR vs. Ambient Temperature. FIGURE 2-14: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85°C. FIGURE 2-16: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125°C. FIGURE 2-17: Input Bias and Offset Currents vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-18: Input Bias Current vs. Input Voltage (Below VSS). 2.2 Other DC Voltages and Currents FIGURE 2-19: Input Common Mode Voltage Headroom (Range) vs. Ambient Temperature. FIGURE 2-20: Output Voltage Headroom vs. Output Current. FIGURE 2-21: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-22: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-23: Supply Current vs. Power Supply Voltage. FIGURE 2-24: Power-On Reset Trip Voltage. FIGURE 2-25: Power-On Reset Voltage vs. Ambient Temperature. 2.3 Frequency Response FIGURE 2-26: CMRR and PSRR vs. Frequency. FIGURE 2-27: Open-Loop Gain vs. Frequency with VDD = 1.8V. FIGURE 2-28: Open-Loop Gain vs. Frequency with VDD = 5.5V. FIGURE 2-29: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. FIGURE 2-30: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage. FIGURE 2-31: Gain Bandwidth Product and Phase Margin vs. Output Voltage. FIGURE 2-32: Closed-Loop Output Impedance vs. Frequency with VDD = 1.8V. FIGURE 2-33: Closed-Loop Output Impedance vs. Frequency with VDD = 5.5V. FIGURE 2-34: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-35: EMIRR vs. Frequency. FIGURE 2-36: EMIRR vs. Input Voltage. FIGURE 2-37: Channel-to-Channel Separation vs. Frequency. 2.4 Input Noise and Distortion FIGURE 2-38: Input Noise Voltage Density and Integrated Input Noise Voltage vs. Frequency. FIGURE 2-39: Input Noise Voltage Density vs. Input Common Mode Voltage. FIGURE 2-40: Intermodulation Distortion vs. Frequency with VCM Disturbance (see Figure 1-6). FIGURE 2-41: Inter-Modulation Distortion vs. Frequency with VDD Disturbance (see Figure 1-6). FIGURE 2-42: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD = 1.8V. FIGURE 2-43: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD = 5.5V. 2.5 Time Response FIGURE 2-44: Input Offset Voltage vs. Time with Temperature Change. FIGURE 2-45: Input Offset Voltage vs. Time at Power-Up. FIGURE 2-46: The MCP6V61/1U/2/4 Family Shows No Input Phase Reversal with Overdrive. FIGURE 2-47: Non-Inverting Small Signal Step Response. FIGURE 2-48: Non-Inverting Large Signal Step Response. FIGURE 2-49: Inverting Small Signal Step Response. FIGURE 2-50: Inverting Large Signal Step Response. FIGURE 2-51: Slew Rate vs. Ambient Temperature. FIGURE 2-52: Output Overdrive Recovery vs. Time with G = -10 V/V. FIGURE 2-53: Output Overdrive Recovery Time vs. Inverting Gain. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Applications 4.1 Overview of Zero-Drift Operation FIGURE 4-1: Simplified Zero-Drift Op Amp Functional Diagram. 4.1.1 Building Blocks 4.1.2 Chopping Action FIGURE 4-2: First Chopping Clock Phase; Equivalent Amplifier Diagram. FIGURE 4-3: Second Chopping Clock Phase; Equivalent Amplifier Diagram. 4.1.3 Intermodulation Distortion (IMD) 4.2 Other Functional Blocks 4.2.1 Rail-to-Rail Inputs FIGURE 4-4: Simplified Analog Input ESD Structures. FIGURE 4-5: Protecting the Analog Inputs Against High Voltages. FIGURE 4-6: Protecting the Analog Inputs Against High Currents. 4.2.2 Rail-to-Rail Output 4.3 Application Tips 4.3.1 Input Offset Voltage Over Temperature 4.3.2 DC Gain Plots 4.3.3 Offset at Power-Up 4.3.4 Source Resistances 4.3.5 Source Capacitance 4.3.6 Capacitive Loads FIGURE 4-7: Output Resistor, RISO, Stabilizes Capacitive Loads. FIGURE 4-8: Recommended RISO values for Capacitive Loads. 4.3.7 Stabilizing Output Loads FIGURE 4-9: Output Load. 4.3.8 Gain Peaking FIGURE 4-10: Amplifier with Parasitic Capacitance. 4.3.9 Reducing Undesired Noise and Signals 4.3.10 Supply Bypassing and Filtering 4.3.11 PCB Design for DC Precision 4.4 Typical Applications 4.4.1 Wheatstone Bridge FIGURE 4-11: Simple Design. 4.4.2 RTD Sensor FIGURE 4-12: RTD Sensor. 4.4.3 Offset Voltage Correction FIGURE 4-13: Offset Correction. 4.4.4 Precision Comparator FIGURE 4-14: Precision Comparator. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information 80 µA, 1 MHz Zero-Drift Op Amps Appendix A: Revision History Revision B (September 2015) Revision A (December 2014) Product Identification System AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Worldwide Sales and Service