Datasheet MCP6V81, MCP6V81U, MCP6V82, MCP6V84 (Microchip) - 8

MCP6V81/1U/2/4 Note:
Unless otherwise indicated, TA = +25°C, VDD = +2.2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 30 pF.
8 60% Representative Part Tester Data 6 V = 5.5V 3355 Samples DD 50% 4 T = +25ºC A V = 5.5V DD 40% ltage (µV) 2 o Occurrences 30% 0 -2 20% T = +125°C A T = +85°C V = 2.2V DD -4 A T = +25°C 10% A Input Offset V T = -40°C -6 A Percentage of 0% -8 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) 1/CMRR (µV/V) FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
Common-Mode Rejection Output Voltage with VDD = 5.5V. Ratio.
8 60% V = 2.2V DD Tester Data 6 Representative Part 50% 3365 Samples 4 T = +25ºC A 40% ltage (µV) 2 o Occurrences 0 30% -2 T = +125°C A T = +85°C 20% A -4 T = +25°C A T = -40°C A 10% Input Offset V -6 Percentage of -8 0% -0.5 -0.2 0.1 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Common-Mode Input Voltage (V) 1/PSRR (µV/V) FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
Power Supply Rejection Common-Mode Voltage with VDD = 2.2V. Ratio.
8 80% V = 5.5V DD Tester Data 6 Representative Part 70% 3355 Samples = 5.5V 4 60% T = +25ºC VDD A ltage (µV) 2 50% o Occurrences 0 40% T = +125°C -2 A 30% T = +85°C A V = 2.2V DD -4 T = +25°C A 20% T = -40°C A Input Offset V -6 10% Percentage of -8 0% -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common-Mode Input Voltage (V) 1/A (µV/V) OL FIGURE 2-9:
Input Offset Voltage vs.
FIGURE 2-12:
DC Open-Loop Gain. Common-Mode Voltage with VDD = 5.5V. DS20005419B-page 8  2016 Microchip Technology Inc. Document Outline 5 MHz, 0.5 mA, Zero-Drift Op Amps Features Typical Applications Design Aids Related Parts Description Package Types Typical Application Circuit FIGURE 1: Input Offset Voltage vs. Ambient Temperature with VDD = 2.2V. FIGURE 2: Input Offset Voltage vs. Ambient Temperature with VDD = 5.5V. 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC Electrical Specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: Temperature Specifications 1.3 Timing Diagrams FIGURE 1-1: Amplifier Start-Up. FIGURE 1-2: Offset Correction Settling Time. FIGURE 1-3: Output Overdrive Recovery. 1.4 Test Circuits FIGURE 1-4: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-5: AC and DC Test Circuit for Most Inverting Gain Conditions. FIGURE 1-6: Test Circuit for Dynamic Input Behavior. 2.0 Typical Performance Curves 2.1 DC Input Precision FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage Quadratic Temperature Coefficient. FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage with VCM = VCML. FIGURE 2-5: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMH. FIGURE 2-6: Input Offset Voltage vs. Output Voltage with VDD = 2.2V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage with VDD = 5.5V. FIGURE 2-8: Input Offset Voltage vs. Common-Mode Voltage with VDD = 2.2V. FIGURE 2-9: Input Offset Voltage vs. Common-Mode Voltage with VDD = 5.5V. FIGURE 2-10: Common-Mode Rejection Ratio. FIGURE 2-11: Power Supply Rejection Ratio. FIGURE 2-12: DC Open-Loop Gain. FIGURE 2-13: CMRR and PSRR vs. Ambient Temperature. FIGURE 2-14: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-15: Input Bias and Offset Currents vs. Common-Mode Input Voltage with TA = +85°C. FIGURE 2-16: Input Bias and Offset Currents vs. Common-Mode Input Voltage with TA = +125°C. FIGURE 2-17: Input Bias and Offset Currents vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-18: Input Bias Current vs. Input Voltage (Below VSS). 2.2 Other DC Voltages and Currents FIGURE 2-19: Input Common-Mode Voltage Headroom (Range) vs. Ambient Temperature. FIGURE 2-20: Output Voltage Headroom vs. Output Current. FIGURE 2-21: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-22: Output Short-Circuit Current vs. Power Supply Voltage. FIGURE 2-23: Supply Current vs. Power Supply Voltage. FIGURE 2-24: Power-on Reset Trip Voltage. FIGURE 2-25: Power-on Reset Voltage vs. Ambient Temperature. 2.3 Frequency Response FIGURE 2-26: CMRR and PSRR vs. Frequency. FIGURE 2-27: Open-Loop Gain vs. Frequency with VDD = 2.2V. FIGURE 2-28: Open-Loop Gain vs. Frequency with VDD = 5.5V. FIGURE 2-29: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. FIGURE 2-30: Gain Bandwidth Product and Phase Margin vs. Common-Mode Input Voltage. FIGURE 2-31: Gain Bandwidth Product and Phase Margin vs. Output Voltage. FIGURE 2-32: Closed-Loop Output Impedance vs. Frequency with VDD = 2.2V. FIGURE 2-33: Closed-Loop Output Impedance vs. Frequency with VDD = 5.5V. FIGURE 2-34: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-35: EMIRR vs. Frequency. FIGURE 2-36: EMIRR vs. Input Voltage. FIGURE 2-37: Channel-to-Channel Separation vs. Frequency. 2.4 Input Noise and Distortion FIGURE 2-38: Input Noise Voltage Density and Integrated Input Noise Voltage vs. Frequency. FIGURE 2-39: Input Noise Voltage Density vs. Input Common-Mode Voltage. FIGURE 2-40: Intermodulation Distortion vs. Frequency with VCM Disturbance (see Figure 1-6). FIGURE 2-41: Intermodulation Distortion vs. Frequency with VDD Disturbance (see Figure 1-6). FIGURE 2-42: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD = 2.2V. FIGURE 2-43: Input Noise vs. Time with 1 Hz and 10 Hz Filters and VDD = 5.5V. 2.5 Time Response FIGURE 2-44: Input Offset Voltage vs. Time with Temperature Change. FIGURE 2-45: Input Offset Voltage vs. Time at Power-Up. FIGURE 2-46: The MCP6V81/1U/2/4 Family Shows No Input Phase Reversal with Overdrive. FIGURE 2-47: Non-Inverting Small Signal Step Response. FIGURE 2-48: Non-Inverting Large Signal Step Response. FIGURE 2-49: Inverting Small Signal Step Response. FIGURE 2-50: Inverting Large Signal Step Response. FIGURE 2-51: Slew Rate vs. Ambient Temperature. FIGURE 2-52: Output Overdrive Recovery vs. Time with G = -10 V/V. FIGURE 2-53: Output Overdrive Recovery Time vs. Inverting Gain. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs (VOUT, VOUTA, VOUTB, VOUTC, VOUTD) 3.2 Analog Inputs (VIN-, VIN+, VINB+, VINB-, VINC-, VINC+, VIND+, VIND-) 3.3 Power Supply Pins (VDD, VSS) 3.4 Exposed Thermal Pad (EP) 4.0 Applications 4.1 Overview of Zero-Drift Operation FIGURE 4-1: Simplified Zero-Drift Op Amp Functional Diagram. FIGURE 4-2: First Chopping Clock Phase; Equivalent Amplifier Diagram. FIGURE 4-3: Second Chopping Clock Phase; Equivalent Amplifier Diagram. 4.2 Other Functional Blocks FIGURE 4-4: Simplified Analog Input ESD Structures. FIGURE 4-5: Protecting the Analog Inputs Against High Voltages. FIGURE 4-6: Protecting the Analog Inputs Against High Currents. 4.3 Application Tips FIGURE 4-7: Output Resistor, RISO, Stabilizes Capacitive Loads. FIGURE 4-8: Recommended RISO values for Capacitive Loads. FIGURE 4-9: Output Load. FIGURE 4-10: Amplifier with Parasitic Capacitance. 4.4 Typical Applications FIGURE 4-11: Simple Design. FIGURE 4-12: RTD Sensor. FIGURE 4-13: Offset Correction. FIGURE 4-14: Precision Comparator. 5.0 Design Aids 5.1 FilterLab® Software 5.2 Microchip Advanced Part Selector (MAPS) 5.3 Analog Demonstration and Evaluation Boards 5.4 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service