Datasheet MCP621S, MCP621S, MCP622, MCP623, MCP624, MCP625, MCP629 (Microchip) - 10
| Manufacturer | Microchip |
| Description | The MCP62x family of operational amplifiers feature low offset |
| Pages / Page | 62 / 10 — MCP621/1S/2/3/4/5/9. Note:. 120. 1.E-03. 100. A E-04. 100µ. ent rr. … |
| File Format / Size | PDF / 2.2 Mb |
| Document Language | English |
MCP621/1S/2/3/4/5/9. Note:. 120. 1.E-03. 100. A E-04. 100µ. ent rr. 1.E-05. 10µ. tude (. 1.E-06. ) 40. fset. agni E-07. 100n. 1.E-08. 10n. ias,. rrent E-09
Model Line for this Datasheet
- MCP6231-E/MC MCP6231-E/MS MCP6231-E/P MCP6231-E/SN MCP6231RT-E/OT MCP6231T-E/MC MCP6231T-E/MS MCP6231T-E/OT MCP6231T-E/OTVAO MCP6231T-E/SN MCP6231UT-E/LT MCP6231UT-E/LTVAO MCP6231UT-E/OT MCP6231UT-E/OTVAO MCP6232-E/MS MCP6232-E/P MCP6232-E/SN MCP6232T-E/MNY MCP6232T-E/MNYVAO MCP6232T-E/MS MCP6232T-E/SN MCP6234-E/P MCP6234-E/SL MCP6234-E/ST MCP6234-E/STVAO MCP6234T-E/SL MCP6234T-E/ST MCP6234T-E/STVAO MCP623T-E/CHY
- MCP624-E/SL MCP624-E/ST MCP6241-E/MC MCP6241-E/MS MCP6241-E/P MCP6241-E/SN MCP6241RT-E/OT MCP6241T-E/MC MCP6241T-E/MS MCP6241T-E/OT MCP6241T-E/OTVAO MCP6241T-E/SN MCP6241UT-E/LT MCP6241UT-E/OT MCP6241UT-E/OTVAO MCP6242-E/MS MCP6242-E/P MCP6242-E/SN MCP6242T-E/MS MCP6242T-E/MSVAO MCP6242T-E/SN MCP6244-E/P MCP6244-E/SL MCP6244-E/ST MCP6244T-E/SL MCP6244T-E/ST MCP6244T-E/STVAO MCP624T-E/SL MCP624T-E/ST MCP624T-E/STVAO
- MCP629-E/ML MCP6291-E/MS MCP6291-E/P MCP6291-E/SN MCP6291RT-E/OT MCP6291T-E/MS MCP6291T-E/OT MCP6291T-E/OTVAO MCP6291T-E/SN MCP6292-E/MS MCP6292-E/P MCP6292-E/SN MCP6292-E/SNVAO MCP6292-H/MS MCP6292T-E/MS MCP6292T-E/MSVAO MCP6292T-E/SN MCP6292T-E/SNVAO MCP6292T-H/MS MCP6293-E/MS MCP6293-E/P MCP6293-E/SN MCP6293T-E/CH MCP6293T-E/MS MCP6293T-E/SN MCP6294-E/P MCP6294-E/SL MCP6294-E/SLVAO MCP6294-E/ST MCP6294-E/STVAO MCP6294T-E/SL MCP6294T-E/SLVAO MCP6294T-E/ST MCP6294T-E/STVAO MCP6295-E/MS MCP6295-E/P MCP6295-E/SN MCP6295T-E/MS MCP6295T-E/SN MCP629T-E/ML
Text Version of Document
MCP621/1S/2/3/4/5/9 Note:
Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.
120 1.E-03 1m s ) 100
IOS
1. A E-04 100µ ent rr 80 1.E-05 10µ u tude ( C 60
Representative Part
1.E-06 1µ ) 40
T
fset A
A = +85°C
1. agni E-07 100n (p
V
20
DD = 5.5V
M Of 1.E-08 10n 0 ias, 1. rrent E-09 1n
+125°C
B u -20
+85°C I
1. C E-10 100p
B +25°C
-40 10p
-40°C
Input 1.E-11 -60 Input1.E-12 1p 5 0 5 0 5 0 5 0 5 0 5 0 5 0 -0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Common Mode Input Voltage (V) Input Voltage (V) FIGURE 2-13:
Input Bias and Offset
FIGURE 2-15:
Input Bias Current vs. Input Currents vs. Common Mode Input Voltage with Voltage (below VSS). TA = +85°C.
1500 s
IOS
nt 1000 rre u
Representative Part
C
T
500
A = +125°C
)
V
fset A
DD = 5.5V
(p , Of 0 ias
IB
B -500 Input -1000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-14:
Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125°C. DS20002188D-page 10 2009-2014 Microchip Technology Inc. Document Outline 20 MHz, 200 µV Op Amps with mCal Features Typical Applications Design Aids Description Typical Application Circuit High Gain-Bandwidth Op Amp Portfolio Package Types 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC Electrical Specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: Digital Electrical Specifications TABLE 1-4: Temperature Specifications 1.3 Timing Diagram FIGURE 1-1: Timing Diagram. 1.4 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves 2.1 DC Signal Inputs FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage Repeatability (repeated calibration). FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-5: Input Offset Voltage vs. Output Voltage. FIGURE 2-6: Low Input Common Mode Voltage Headroom vs. Ambient Temperature. FIGURE 2-7: High Input Common Mode Voltage Headroom vs. Ambient Temperature. FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 2.5V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V. FIGURE 2-10: CMRR and PSRR vs. Ambient Temperature. FIGURE 2-11: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-12: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V. FIGURE 2-13: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85°C. FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125°C. FIGURE 2-15: Input Bias Current vs. Input Voltage (below VSS). 2.2 Other DC Voltages and Currents FIGURE 2-16: Ratio of Output Voltage Headroom to Output Current. FIGURE 2-17: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-18: Output Short-Circuit Current vs. Power Supply Voltage. FIGURE 2-19: Supply Current vs. Power Supply Voltage. FIGURE 2-20: Supply Current vs. Common Mode Input Voltage. FIGURE 2-21: Power-On Reset Voltages vs. Ambient Temperature. FIGURE 2-22: Normalized Internal Calibration Voltage. FIGURE 2-23: VCAL Input Resistance vs. Temperature. 2.3 Frequency Response FIGURE 2-24: CMRR and PSRR vs. Frequency. FIGURE 2-25: Open-Loop Gain vs. Frequency. FIGURE 2-26: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. FIGURE 2-27: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage. FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Output Voltage. FIGURE 2-29: Closed-Loop Output Impedance vs. Frequency. FIGURE 2-30: Gain Peaking vs. Normalized Capacitive Load. FIGURE 2-31: Channel-to-Channel Separation vs. Frequency. 2.4 Input Noise and Distortion FIGURE 2-32: Input Noise Voltage Density vs. Frequency. FIGURE 2-33: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 100 Hz. FIGURE 2-34: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 1 MHz. FIGURE 2-35: Input Noise plus Offset vs. Time with 0.1 Hz Filter. FIGURE 2-36: THD+N vs. Frequency. 2.5 Time Response FIGURE 2-37: Non-Inverting Small Signal Step Response. FIGURE 2-38: Non-Inverting Large Signal Step Response. FIGURE 2-39: Inverting Small Signal Step Response. FIGURE 2-40: Inverting Large Signal Step Response. FIGURE 2-41: The MCP621/1S/2/3/4/5/9 Family Shows No Input Phase Reversal with Overdrive. FIGURE 2-42: Slew Rate vs. Ambient Temperature. FIGURE 2-43: Maximum Output Voltage Swing vs. Frequency. 2.6 Calibration and Chip Select Response FIGURE 2-44: CAL/CS Current vs. Power Supply Voltage. FIGURE 2-45: CAL/CS Voltage, Output Voltage and Supply Current (for Side A) vs. Time with VDD = 2.5V. FIGURE 2-46: CAL/CS Voltage, Output Voltage and Supply Current (for Side A) vs. Time with VDD = 5.5V. FIGURE 2-47: CAL/CS Hysteresis vs. Ambient Temperature. FIGURE 2-48: CAL/CS Turn-On Time vs. Ambient Temperature. FIGURE 2-49: CAL/CS’s Pull-Down Resistor (RPD) vs. Ambient Temperature. FIGURE 2-50: Quiescent Current in Shutdown vs. Power Supply Voltage. FIGURE 2-51: Output Leakage Current vs. Output Voltage. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Calibration Common Mode Voltage Input 3.5 Calibrate/Chip Select Digital Input 3.6 Exposed Thermal Pad (EP) 4.0 Applications 4.1 Calibration and Chip Select FIGURE 4-1: Common-Mode Reference’s Input Circuitry. FIGURE 4-2: Setting VCM with External Resistors. 4.2 Input FIGURE 4-3: Simplified Analog Input ESD Structures. FIGURE 4-4: Protecting the Analog Inputs. FIGURE 4-5: Unity Gain Voltage Limitations for Linear Operation. 4.3 Rail-to-Rail Output FIGURE 4-6: Output Current. FIGURE 4-7: Diagram for Resistive Load Power Calculations. FIGURE 4-8: Diagram for Capacitive Load Power Calculations. 4.4 Improving Stability FIGURE 4-9: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-10: Recommended RISO Values for Capacitive Loads. FIGURE 4-11: Amplifier with Parasitic Capacitance. FIGURE 4-12: Maximum Recommended RF vs. Gain. 4.5 Power Supply 4.6 High Speed PCB Layout 4.7 Typical Applications FIGURE 4-13: Power Driver. FIGURE 4-14: Transimpedance Amplifier for an Optical Detector. FIGURE 4-15: H-Bridge Driver. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service
Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.
120 1.E-03 1m s ) 100
IOS
1. A E-04 100µ ent rr 80 1.E-05 10µ u tude ( C 60
Representative Part
1.E-06 1µ ) 40
T
fset A
A = +85°C
1. agni E-07 100n (p
V
20
DD = 5.5V
M Of 1.E-08 10n 0 ias, 1. rrent E-09 1n
+125°C
B u -20
+85°C I
1. C E-10 100p
B +25°C
-40 10p
-40°C
Input 1.E-11 -60 Input1.E-12 1p 5 0 5 0 5 0 5 0 5 0 5 0 5 0 -0. 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Common Mode Input Voltage (V) Input Voltage (V) FIGURE 2-13:
Input Bias and Offset
FIGURE 2-15:
Input Bias Current vs. Input Currents vs. Common Mode Input Voltage with Voltage (below VSS). TA = +85°C.
1500 s
IOS
nt 1000 rre u
Representative Part
C
T
500
A = +125°C
)
V
fset A
DD = 5.5V
(p , Of 0 ias
IB
B -500 Input -1000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-14:
Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125°C. DS20002188D-page 10 2009-2014 Microchip Technology Inc. Document Outline 20 MHz, 200 µV Op Amps with mCal Features Typical Applications Design Aids Description Typical Application Circuit High Gain-Bandwidth Op Amp Portfolio Package Types 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC Electrical Specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: Digital Electrical Specifications TABLE 1-4: Temperature Specifications 1.3 Timing Diagram FIGURE 1-1: Timing Diagram. 1.4 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves 2.1 DC Signal Inputs FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage Repeatability (repeated calibration). FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-5: Input Offset Voltage vs. Output Voltage. FIGURE 2-6: Low Input Common Mode Voltage Headroom vs. Ambient Temperature. FIGURE 2-7: High Input Common Mode Voltage Headroom vs. Ambient Temperature. FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 2.5V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V. FIGURE 2-10: CMRR and PSRR vs. Ambient Temperature. FIGURE 2-11: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-12: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V. FIGURE 2-13: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85°C. FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125°C. FIGURE 2-15: Input Bias Current vs. Input Voltage (below VSS). 2.2 Other DC Voltages and Currents FIGURE 2-16: Ratio of Output Voltage Headroom to Output Current. FIGURE 2-17: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-18: Output Short-Circuit Current vs. Power Supply Voltage. FIGURE 2-19: Supply Current vs. Power Supply Voltage. FIGURE 2-20: Supply Current vs. Common Mode Input Voltage. FIGURE 2-21: Power-On Reset Voltages vs. Ambient Temperature. FIGURE 2-22: Normalized Internal Calibration Voltage. FIGURE 2-23: VCAL Input Resistance vs. Temperature. 2.3 Frequency Response FIGURE 2-24: CMRR and PSRR vs. Frequency. FIGURE 2-25: Open-Loop Gain vs. Frequency. FIGURE 2-26: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. FIGURE 2-27: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage. FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Output Voltage. FIGURE 2-29: Closed-Loop Output Impedance vs. Frequency. FIGURE 2-30: Gain Peaking vs. Normalized Capacitive Load. FIGURE 2-31: Channel-to-Channel Separation vs. Frequency. 2.4 Input Noise and Distortion FIGURE 2-32: Input Noise Voltage Density vs. Frequency. FIGURE 2-33: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 100 Hz. FIGURE 2-34: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 1 MHz. FIGURE 2-35: Input Noise plus Offset vs. Time with 0.1 Hz Filter. FIGURE 2-36: THD+N vs. Frequency. 2.5 Time Response FIGURE 2-37: Non-Inverting Small Signal Step Response. FIGURE 2-38: Non-Inverting Large Signal Step Response. FIGURE 2-39: Inverting Small Signal Step Response. FIGURE 2-40: Inverting Large Signal Step Response. FIGURE 2-41: The MCP621/1S/2/3/4/5/9 Family Shows No Input Phase Reversal with Overdrive. FIGURE 2-42: Slew Rate vs. Ambient Temperature. FIGURE 2-43: Maximum Output Voltage Swing vs. Frequency. 2.6 Calibration and Chip Select Response FIGURE 2-44: CAL/CS Current vs. Power Supply Voltage. FIGURE 2-45: CAL/CS Voltage, Output Voltage and Supply Current (for Side A) vs. Time with VDD = 2.5V. FIGURE 2-46: CAL/CS Voltage, Output Voltage and Supply Current (for Side A) vs. Time with VDD = 5.5V. FIGURE 2-47: CAL/CS Hysteresis vs. Ambient Temperature. FIGURE 2-48: CAL/CS Turn-On Time vs. Ambient Temperature. FIGURE 2-49: CAL/CS’s Pull-Down Resistor (RPD) vs. Ambient Temperature. FIGURE 2-50: Quiescent Current in Shutdown vs. Power Supply Voltage. FIGURE 2-51: Output Leakage Current vs. Output Voltage. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Calibration Common Mode Voltage Input 3.5 Calibrate/Chip Select Digital Input 3.6 Exposed Thermal Pad (EP) 4.0 Applications 4.1 Calibration and Chip Select FIGURE 4-1: Common-Mode Reference’s Input Circuitry. FIGURE 4-2: Setting VCM with External Resistors. 4.2 Input FIGURE 4-3: Simplified Analog Input ESD Structures. FIGURE 4-4: Protecting the Analog Inputs. FIGURE 4-5: Unity Gain Voltage Limitations for Linear Operation. 4.3 Rail-to-Rail Output FIGURE 4-6: Output Current. FIGURE 4-7: Diagram for Resistive Load Power Calculations. FIGURE 4-8: Diagram for Capacitive Load Power Calculations. 4.4 Improving Stability FIGURE 4-9: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-10: Recommended RISO Values for Capacitive Loads. FIGURE 4-11: Amplifier with Parasitic Capacitance. FIGURE 4-12: Maximum Recommended RF vs. Gain. 4.5 Power Supply 4.6 High Speed PCB Layout 4.7 Typical Applications FIGURE 4-13: Power Driver. FIGURE 4-14: Transimpedance Amplifier for an Optical Detector. FIGURE 4-15: H-Bridge Driver. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service
