Datasheet Summary SAM D21EL, SAM D21GL (Microchip) - 8

ManufacturerMicrochip
Description32-bit ARM-Based Microcontrollers
Pages / Page38 / 8 — 32-bit ARM-Based Microcontrollers. Table 3-1. SAM D21L Device …
Revision02-01-2017
File Format / SizePDF / 851 Kb
Document LanguageEnglish

32-bit ARM-Based Microcontrollers. Table 3-1. SAM D21L Device Identification Values. Device Variant. DID.DEVSEL

32-bit ARM-Based Microcontrollers Table 3-1. SAM D21L Device Identification Values Device Variant DID.DEVSEL

Model Line for this Datasheet

ATSAMD21E15
ATSAMD21E15L
ATSAMD21E16
ATSAMD21E16L
ATSAMD21E17
ATSAMD21E18
ATSAMD21G15
ATSAMD21G16
ATSAMD21G16L
ATSAMD21G17
ATSAMD21G18
ATSAMD21J15
ATSAMD21J16
ATSAMD21J17
ATSAMD21J18

Text Version of Document

32-bit ARM-Based Microcontrollers Table 3-1. SAM D21L Device Identification Values Device Variant DID.DEVSEL Device ID (DID)
Reserved 0x00 - 0x61 SAMD21E16L 0x62 0x1001143E SAMD21E15L 0x63 0x1001143F Reserved 0x64 - 0x86 SAMD21G16L 0x87 0x10011457 Reserved 0x88 - 0xFF
Note: 
The device variant (last letter of the ordering number) is independent of the die revision (DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of the die. The device variant denotes functional differences, whereas the die revision marks evolution of the die. © 2017 Microchip Technology Inc.
Datasheet Summary
40001885A-page 8 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 3.1. SAM D21ExL 3.2. SAM D21GxL 3.3. Device Identification 4. Block Diagram 5. Pinout 5.1. SAM D21GxL 5.1.1. QFN48 5.2. SAM D21ExL 5.2.1. QFN32 / TQFP32 6. Product Mapping 7. Processor And Architecture 7.1. Cortex M0+ Processor 7.1.1. Cortex M0+ Configuration 7.1.2. Cortex-M0+ Peripherals 7.1.3. Cortex-M0+ Address Map 7.1.4. I/O Interface 7.1.4.1. Overview 7.1.4.2. Description 7.2. Nested Vector Interrupt Controller 7.2.1. Overview 7.2.2. Interrupt Line Mapping 7.3. Micro Trace Buffer 7.3.1. Features 7.3.2. Overview 7.4. High-Speed Bus System 7.4.1. Features 7.4.2. Configuration 7.4.3. SRAM Quality of Service 7.5. AHB-APB Bridge 7.6. PAC - Peripheral Access Controller 7.6.1. Overview 7.6.2. Register Description 7.6.2.1. PAC0 Register Description 7.6.2.1.1. Write Protect Clear 7.6.2.1.2. Write Protect Set 7.6.2.2. PAC1 Register Description 7.6.2.2.1. Write Protect Clear 7.6.2.2.2. Write Protect Set 7.6.2.3. PAC2 Register Description 7.6.2.3.1. Write Protect Clear 7.6.2.3.2. Write Protect Set 8. Packaging Information 8.1. Thermal Considerations 8.1.1. Thermal Resistance Data 8.1.2. Junction Temperature 8.2. Package Drawings 8.2.1. 48 pin QFN 8.2.2. 32 pin TQFP 8.2.3. 32 pin QFN 8.3. Soldering Profile The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service