Datasheet PIC16F1773, PIC16F1776, PIC16LF1773, PIC16LF1776 (Microchip) - 5

PIC16(L)F1773/6 PIN ALLOCATION TABLES TABLE 3: 28-PIN ALLOCATION TABLE (PIC16(L)F1773/6) P O S e S N nc F or t OIC/ re p fe at r p e c O /S UQ D e ar I/ IP m rru in p Am asi D PRG ZC ADC e R m DAC Ti te B P -P Op 8 o In S 2 ltag C in o V -P 28
RA0 2 27 — — AN0 — C1IN0- — — — IOCA0 — C2IN0- C3IN0- C4IN0- C5IN0- C6IN0- RA1 3 28 PRG1IN0 — AN1 — C1IN1- OPA1OUT — — IOCA1 — PRG2IN1 C2IN1- OPA2IN1+ C3IN1- OPA2IN1- C4IN1- RA2 4 1 — — AN2 DAC1REF0- C1IN0+ — DAC1OUT1 — IOCA2 — VREF- DAC2REF0- C2IN0+ DAC3REF0- C3IN0+ DAC4REF0- C4IN0+ DAC5REF0- C5IN0+ DAC7REF0- C6IN0+ RA3 5 2 — — AN3 DAC1REF0+ C1IN1+ — — — IOCA3 — VREF+ DAC2REF0+ DAC3REF0+ DAC4REF0+ DAC5REF0+ DAC7REF0+ RA4 6 3 — — — — — OPA1IN0+ DAC4OUT1 T0CKI IOCA4 — RA5 7 4 — — AN4 — — OPA1IN0- DAC2OUT1 — IOCA5 — RA6 10 7 — — — — CLKOUT — — — IOCA6 OSC2 C6IN1+ RA7 9 6 — — — — CLKIN — — — IOCA7 OSC1 RB0 21 18 — ZCD AN12 HIB0 C2IN1+ — — — IOCB0 — RB1 22 19 PRG1IN1 — AN10 HIB1 C1IN3- OPA2OUT — — IOCB1 — PRG2IN0 C2IN3- OPA1IN1+ C3IN3- OPA1IN1- C4IN3- RB2 23 20 — — AN8 — — OPA2IN0- DAC3OUT1 — IOCB2 — RB3 24 21 — — AN9 — C1IN2- OPA2IN0+ — — IOCB3 — C2IN2- C3IN2- RB4 25 22 — — AN11 — C3IN1+ — — T5G IOCB4 — RB5 26 23 — — AN13 DAC5REF1- C4IN2- — — T1G IOCB5 — DAC7REF1- RB6 27 24 — — — DAC5REF1+ C4IN1+ — — — IOCB6 ICSPCLK DAC7REF1+ ICDCLK RB7 28 25 — — — — C5IN1+ — DAC1OUT2 T6IN IOCB7 ICSPDAT DAC2OUT2 ICDDAT DAC5OUT2 DAC3OUT2 DAC4OUT2 DAC7OUT2 RC0 11 8 — — — — — — DAC5OUT1 T1CKI IOCC0 — T3CKI T3G RC1 12 9 — — — — — — DAC7OUT1 — IOCC1 —  2015-2016 Microchip Technology Inc. DS40001810B-page 5 Document Outline Description Core Features Memory Operating Characteristics eXtreme Low-Power (XLP) Features Intelligent Analog Peripherals Digital Peripherals Clocking Structure TABLE 1: PIC16(L)F1773/6/7/8/9 Family Types TABLE 2: Packages Pin Diagrams FIGURE 1: 28-Pin SPDIP, SOIC, SSOP FIGURE 2: 28-Pin UQFN (6x6x0.5 mm) Pin Allocation Tables TABLE 3: 28-Pin Allocation Table (PIC16(L)F1773/6) Table of Contents Most Current Data Sheet Errata Customer Notification System 1.0 Device Overview TABLE 1-1: Device Peripheral Summary 1.1 Register and Bit naming conventions EXAMPLE 1-1: EXAMPLE 1-2: FIGURE 1-1: PIC16(L)F1773/6 Block Diagram TABLE 1-2: PIC16(L)F1773/6 PinOut Description 1.2 Peripheral Connection Matrix TABLE 1-3: Peripheral Connection Matrix 2.0 Enhanced Mid-Range CPU FIGURE 2-1: Core Block Diagram 2.1 Automatic Interrupt Context Saving 2.2 16-Level Stack with Overflow and Underflow 2.3 File Select Registers 2.4 Instruction Set 3.0 Memory Organization 3.1 Program Memory Organization 3.2 High-Endurance Flash TABLE 3-1: Device Sizes and Addresses FIGURE 3-1: Program Memory Map and Stack for PIC16(L)F1773 FIGURE 3-2: Program Memory Map and Stack for PIC16(L)F1776 EXAMPLE 3-1: RETLW Instruction EXAMPLE 3-2: Accessing Program Memory Via FSR 3.3 Data Memory Organization TABLE 3-2: Core Registers 3.4 Register Definitions: Status Register 3-1: STATUS: STATUS Register FIGURE 3-3: Banked Memory Partitioning TABLE 3-3: PIC16(L)F1773 Memory Map (Banks 0-7) TABLE 3-4: PIC16(L)F1776 Memory Map (Banks 0-7) TABLE 3-5: PIC16(L)F1773 Memory Map, Bank 8-15 TABLE 3-6: PIC16(L)F1776 Memory Map, Bank 8-15 TABLE 3-7: PIC16(L)F1773/6 Memory Map, Bank 16-23 TABLE 3-8: PIC16(L)F1773/6 Memory Map, Bank 24-31 TABLE 3-9: PIC16(L)F1773/6 Memory Map, Bank 27-30 TABLE 3-10: PIC16(L)F1773/6 Memory Map, Bank 31 TABLE 3-11: Core Function Registers Summary(1) TABLE 3-12: Special Function Register Summary 3.5 PCL and PCLATH FIGURE 3-4: Loading of PC in Different Situations 3.6 Stack FIGURE 3-5: Accessing the Stack Example 1 FIGURE 3-6: Accessing the Stack Example 2 FIGURE 3-7: Accessing the Stack Example 3 FIGURE 3-8: Accessing the Stack Example 4 3.7 Indirect Addressing FIGURE 3-9: Indirect Addressing FIGURE 3-10: Traditional Data Memory Map FIGURE 3-11: Linear Data Memory Map FIGURE 3-12: Program Flash Memory Map 4.0 Device Configuration 4.1 Configuration Words 4.2 Register Definitions: Configuration Words Register 4-1: CONFIG1: Configuration Word 1 Register 4-2: CONFIG2: Configuration Word 2 4.3 Code Protection 4.4 Write Protection 4.5 User ID 4.6 Device ID and Revision ID 4.7 Register Definitions: Device and Revision Register 4-3: DevID: Device ID Register Register 4-4: RevID: Revision ID Register 5.0 Oscillator Module (with Fail-Safe Clock Monitor) 5.1 Overview FIGURE 5-1: Simplified PIC® MCU Clock Source Block Diagram 5.2 Clock Source Types FIGURE 5-2: External Clock (EC) Mode Operation FIGURE 5-3: Quartz Crystal Operation (LP, XT or HS Mode) FIGURE 5-4: Ceramic Resonator Operation (XT or HS Mode) FIGURE 5-5: Quartz Crystal Operation (Secondary Oscillator) FIGURE 5-6: External RC Modes FIGURE 5-7: Internal Oscillator Switch Timing 5.3 Clock Switching 5.4 Two-Speed Clock Start-up Mode TABLE 5-1: Oscillator Switching Delays FIGURE 5-8: Two-Speed Start-up 5.5 Fail-Safe Clock Monitor FIGURE 5-9: FSCM Block Diagram FIGURE 5-10: FSCM Timing Diagram 5.6 Register Definitions: Oscillator Control Register 5-1: OSCCON: Oscillator Control Register Register 5-2: OSCSTAT: Oscillator Status Register Register 5-3: OSCTUNE: Oscillator Tuning Register TABLE 5-2: Summary of Registers Associated with Clock Sources TABLE 5-3: Summary of Configuration Word with Clock Sources 6.0 Resets FIGURE 6-1: Simplified Block Diagram of On-Chip Reset Circuit 6.1 Power-On Reset (POR) 6.2 Brown-Out Reset (BOR) TABLE 6-1: BOR Operating Modes FIGURE 6-2: Brown-Out Situations 6.3 Register Definitions: BOR Control Register 6-1: BORCON: Brown-Out Reset Control Register 6.4 Low-Power Brown-Out Reset (LPBOR) 6.5 MCLR TABLE 6-2: MCLR Configuration 6.6 Watchdog Timer (WDT) Reset 6.7 RESET Instruction 6.8 Stack Overflow/Underflow Reset 6.9 Programming Mode Exit 6.10 Power-Up Timer 6.11 Start-up Sequence FIGURE 6-3: Reset Start-up Sequence 6.12 Determining the Cause of a Reset TABLE 6-3: Reset Status Bits and Their Significance TABLE 6-4: Reset Condition for Special Registers 6.13 Power Control (PCON) Register 6.14 Register Definitions: Power Control Register 6-2: PCON: Power Control Register TABLE 6-5: Summary of Registers Associated with Resets 7.0 Interrupts FIGURE 7-1: Interrupt Logic 7.1 Operation 7.2 Interrupt Latency FIGURE 7-2: Interrupt Latency FIGURE 7-3: INT Pin Interrupt Timing 7.3 Interrupts During Sleep 7.4 INT Pin 7.5 Automatic Context Saving 7.6 Register Definitions: Interrupt Control Register 7-1: INTCON: Interrupt Control Register Register 7-2: PIE1: Peripheral Interrupt Enable Register 1 Register 7-3: PIE2: Peripheral Interrupt Enable Register 2 Register 7-4: PIE3: Peripheral Interrupt Enable Register 3 Register 7-5: PIE4: Peripheral Interrupt Enable Register 4 Register 7-6: PIE5: Peripheral Interrupt Enable Register 5 Register 7-7: PIE6: Peripheral Interrupt Enable Register 6 Register 7-8: PIR1: Peripheral Interrupt Request Register 1 Register 7-9: PIR2: Peripheral Interrupt Request Register 2 Register 7-10: PIR3: Peripheral Interrupt Request Register 3 Register 7-11: PIR4: Peripheral Interrupt Request Register 4 Register 7-12: PIR5: Peripheral Interrupt Request Register 5 Register 7-13: PIR6: Peripheral Interrupt Request Register 6 TABLE 7-1: Summary of Registers Associated with Interrupts 8.0 Power-Down Mode (Sleep) 8.1 Wake-up from Sleep FIGURE 8-1: Wake-Up From Sleep Through Interrupt 8.2 Low-Power Sleep Mode 8.3 Register Definitions: Voltage Regulator Control Register 8-1: VREGCON: Voltage Regulator Control Register(1) TABLE 8-1: Summary of Registers Associated with Power-Down Mode 9.0 Watchdog Timer (WDT) FIGURE 9-1: Watchdog Timer Block Diagram 9.1 Independent Clock Source 9.2 WDT Operating Modes TABLE 9-1: WDT Operating Modes 9.3 Time-Out Period 9.4 Clearing the WDT 9.5 Operation During Sleep TABLE 9-2: WDT Clearing Conditions 9.6 Register Definitions: Watchdog Control Register 9-1: WDTCON: Watchdog Timer Control Register TABLE 9-3: Summary of Registers Associated with Watchdog Timer TABLE 9-4: Summary of Configuration Word with Watchdog Timer 10.0 Flash Program Memory Control 10.1 PMADRL and PMADRH Registers 10.2 Flash Program Memory Overview TABLE 10-1: Flash Memory Organization By Device FIGURE 10-1: Flash Program Memory Read Flowchart FIGURE 10-2: Flash Program Memory Read Cycle Execution EXAMPLE 10-1: Flash Program Memory Read FIGURE 10-3: Flash Program Memory Unlock Sequence Flowchart FIGURE 10-4: Flash Program Memory Erase Flowchart EXAMPLE 10-2: Erasing One Row of Program Memory FIGURE 10-5: Block Writes to Flash Program Memory With 32 write latches FIGURE 10-6: Flash Program Memory Write Flowchart EXAMPLE 10-3: Writing to Flash Program Memory 10.3 Modifying Flash Program Memory FIGURE 10-7: Flash Program Memory Modify Flowchart 10.4 User ID, Device ID and Configuration Word Access TABLE 10-2: User ID, Device ID and Configuration Word Access (CFGS = 1) EXAMPLE 10-4: Configuration Word and Device ID Access 10.5 Write/Verify FIGURE 10-8: Flash Program Memory Verify Flowchart 10.6 Register Definitions: Flash Program Memory Control Register 10-1: PMDATL: Program Memory Data Low Byte Register Register 10-2: PMDATH: Program Memory Data High Byte Register Register 10-3: PMADRL: Program Memory Address Low Byte Register Register 10-4: PMADRH: Program Memory Address High Byte Register Register 10-5: PMCON1: Program Memory Control 1 Register Register 10-6: PMCON2: Program Memory Control 2 Register TABLE 10-3: Summary of Registers Associated with Flash Program Memory TABLE 10-4: Summary of Configuration Word with Flash Program Memory 11.0 I/O Ports TABLE 11-1: Port Availability Per Device FIGURE 11-1: Generic I/O Port Operation 11.1 PORTA Registers EXAMPLE 11-1: Initializing PORTA 11.2 Register Definitions: PORTA Register 11-1: PORTA: PORTA Register Register 11-2: TRISA: PORTA Tri-State Register Register 11-3: LATA: PORTA Data Latch Register Register 11-4: ANSELA: PORTA Analog Select Register Register 11-5: WPUA: Weak Pull-Up PORTA Register Register 11-6: ODCONA: PORTA Open-Drain Control Register Register 11-7: SLRCONA: PORTA Slew Rate Control Register Register 11-8: INLVLA: PORTA Input Level Control Register TABLE 11-2: Summary of Registers Associated with PORTA TABLE 11-3: Summary of Configuration Word with PORTA 11.3 PORTB Registers 11.4 Register Definitions: PORTB Register 11-9: PORTB: PORTB Register Register 11-10: TRISB: PORTB Tri-State Register Register 11-11: LATB: PORTB Data Latch Register Register 11-12: ANSELB: PORTB Analog Select Register Register 11-13: WPUB: Weak Pull-Up PORTB Register Register 11-14: ODCONB: PORTB Open-Drain Control Register Register 11-15: SLRCONB: PORTB Slew Rate Control Register Register 11-16: INLVLB: PORTB Input Level Control Register Register 11-17: HIDRVB: PORTB High Drive Control Register TABLE 11-4: Summary of Registers Associated with PORTB 11.5 PORTC Registers 11.6 Register Definitions: PORTC Register 11-18: PORTC: PORTC Register Register 11-19: TRISC: PORTC Tri-State Register Register 11-20: LATC: PORTC Data Latch Register Register 11-21: ANSELC: PORTC Analog Select Register Register 11-22: WPUC: Weak Pull-Up PORTC Register Register 11-23: ODCONC: PORTC Open-Drain Control Register Register 11-24: SLRCONC: PORTC Slew Rate Control Register Register 11-25: INLVLC: PORTC Input Level Control Register TABLE 11-5: Summary of Registers Associated with PORTC 11.7 PORTE Registers Register 11-26: PORTE: PORTE Register 11.8 Register Definitions: PORTE Register 11-27: TRISE: PORTE Tri-State Register Register 11-28: WPUE: Weak Pull-Up PORTE Register Register 11-29: INLVLE: PORTE Input Level Control Register TABLE 11-6: Summary of Registers Associated with PORTE 12.0 Peripheral Pin Select (PPS) Module 12.1 PPS Inputs 12.2 PPS Outputs FIGURE 12-1: Simplified PPS Block Diagram 12.3 Bidirectional Pins 12.4 PPS Lock EXAMPLE 12-1: PPS Lock/Unlock Sequence 12.5 PPS Permanent Lock 12.6 Operation During Sleep 12.7 Effects of a Reset 12.8 Register Definitions: PPS Input Selection Register 12-1: xxxPPS: Peripheral xxx input Selection Register 12-2: RxyPPS: Pin Rxy Output Source Selection Register Register 12-3: PPSLOCK: PPS Lock Register TABLE 12-1: PPS Input register reset values TABLE 12-2: Available PORTS for output by peripheral(2) TABLE 12-3: Summary of Registers Associated with the PPS Module 13.0 Interrupt-On-Change 13.1 Enabling the Module 13.2 Individual Pin Configuration 13.3 Interrupt Flags 13.4 Clearing Interrupt Flags EXAMPLE 13-1: Clearing Interrupt Flags (PORTA Example) 13.5 Operation in Sleep FIGURE 13-1: Interrupt-On-Change Block Diagram (PORTA Example) 13.6 Register Definitions: Interrupt-on-Change Control Register 13-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register Register 13-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register Register 13-3: IOCAF: Interrupt-on-Change PORTA Flag Register Register 13-4: IOCBP: Interrupt-on-Change PORTB Positive Edge Register Register 13-5: IOCBN: Interrupt-on-Change PORTB Negative Edge Register Register 13-6: IOCBF: Interrupt-on-Change PORTB Flag Register Register 13-7: IOCCP: Interrupt-on-Change PORTC Positive Edge Register Register 13-8: IOCCN: Interrupt-on-Change PORTC Negative Edge Register Register 13-9: IOCCF: Interrupt-on-Change PORTC Flag Register Register 13-10: IOCEP: Interrupt-on-Change PORTE Positive Edge Register Register 13-11: IOCEN: Interrupt-on-Change PORTE Negative Edge Register Register 13-12: IOCEF: Interrupt-on-Change PORTE Flag Register TABLE 13-1: Summary of Registers Associated with Interrupt-On-Change 14.0 Fixed Voltage Reference (FVR) 14.1 Independent Gain Amplifiers 14.2 FVR Stabilization Period 14.3 FVR Buffer Stabilization Period FIGURE 14-1: Voltage Reference Block Diagram TABLE 14-1: Peripherals Requiring the Fixed Voltage Reference (FVR) 14.4 Register Definitions: FVR Control Register 14-1: FVRCON: Fixed Voltage Reference Control Register TABLE 14-2: Summary of Registers Associated with Fixed Voltage Reference 15.0 Temperature Indicator Module 15.1 Circuit Operation EQUATION 15-1: Vout Ranges FIGURE 15-1: Temperature Circuit Diagram 15.2 Minimum Operating Vdd TABLE 15-1: Recommended Vdd vs. Range 15.3 Temperature Output 15.4 ADC Acquisition Time TABLE 15-2: Summary of Registers Associated with the Temperature Indicator 16.0 Analog-to-Digital Converter (ADC) Module FIGURE 16-1: ADC Block Diagram 16.1 ADC Configuration TABLE 16-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies FIGURE 16-2: Analog-to-Digital Conversion Tad Cycles FIGURE 16-3: 10-Bit ADC Conversion Result Format 16.2 ADC Operation TABLE 16-2: Auto-Conversion Sources EXAMPLE 16-1: ADC Conversion 16.3 Register Definitions: ADC Control Register 16-1: ADCON0: ADC Control Register 0 Register 16-2: ADCON1: ADC Control Register 1 Register 16-3: ADCON2: ADC Control Register 2 Register 16-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 0 Register 16-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0 Register 16-6: ADRESH: ADC Result Register High (ADRESH) ADFM = 1 Register 16-7: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1 16.4 ADC Acquisition Requirements EQUATION 16-1: Acquisition Time Example(1,2,3) FIGURE 16-4: Analog Input Model FIGURE 16-5: ADC Transfer Function TABLE 16-3: Summary of Registers Associated with ADC 17.0 5-Bit Digital-to-Analog Converter (DAC) Module TABLE 17-1: Available 5-bit DACs 17.1 Output Voltage Selection EQUATION 17-1: DAC Output Voltage 17.2 Ratiometric Output Level 17.3 DAC Voltage Reference Output FIGURE 17-1: Digital-to-Analog Converter Block Diagram FIGURE 17-2: Voltage Reference Output Buffer Example 17.4 Operation During Sleep 17.5 Effects of a Reset 17.6 Register Definitions: DAC Control TABLE 17-2: Register 17-1: DACxCON0: DACx Control Register 0 Register 17-2: DACxREF: DACx Reference Voltage Output Select Register TABLE 17-3: Summary of Registers Associated with the DACx Module 18.0 10-bit Digital-to-Analog Converter (DAC) Module TABLE 18-1: Available 10-bit DACs 18.1 Output Voltage Level Selection 18.2 Ratiometric Output Voltage 18.3 DAC Output 18.4 DAC Reference Selection Justification EQUATION 18-1: DAC Output Voltage FIGURE 18-1: DAC Justification FIGURE 18-2: Digital-to-Analog Converter Block Diagram FIGURE 18-3: Voltage Reference Output Buffer Example 18.5 Operation During Sleep 18.6 Effects of a Reset 18.7 Register Definitions: DAC Control TABLE 18-2: Register 18-1: DACxCON0: DAC Control Register 0 Register 18-2: DACxREFH: DAC Reference Voltage Select High Register Register 18-3: DACxREFL: DAC Reference Voltage Select Low Register Register 18-4: DACLD: DAC Buffer Load Register TABLE 18-3: Summary of Registers Associated with the DACx Module 19.0 Comparator Module 19.1 Comparator Overview TABLE 19-1: Available Comparators FIGURE 19-1: Single Comparator FIGURE 19-2: Comparator Module Simplified Block Diagram 19.2 Comparator Control TABLE 19-2: Comparator Output State vs. Input Conditions 19.3 Comparator Hysteresis 19.4 Timer1 Gate Operation 19.5 Comparator Interrupt 19.6 Comparator Positive Input Selection 19.7 Comparator Negative Input Selection 19.8 Comparator Response Time 19.9 Zero Latency Filter FIGURE 19-3: Comparator Zero Latency Filter Operation 19.10 Analog Input Connection Considerations FIGURE 19-4: Analog Input Model 19.11 Register Definitions: Comparator Control TABLE 19-3: Register 19-1: CMxCON0: Comparator Cx Control Register 0 Register 19-2: CMxCON1: Comparator Cx Control Register 1 Register 19-3: CMxNSEL: Comparator Cx Negative channel Select Register TABLE 19-4: Negative Input Sources Register 19-4: CMxPSEL: Comparator Cx Positive Channel Select Register 1 TABLE 19-5: Positive Input Sources Register 19-5: CMOUT: Comparator Output Register TABLE 19-6: Summary of Registers Associated with Comparator Module TABLE 19-4: Summary of Registers Associated with Comparator Module (Cont.) 20.0 Zero-Cross Detection (ZCD) Module 20.1 External Resistor Selection EQUATION 20-1: External Resistor FIGURE 20-1: External Voltage FIGURE 20-2: Simplified ZCD Block Diagram 20.2 ZCD Logic Output 20.3 ZCD Logic Polarity 20.4 ZCD Interrupts 20.5 Correcting for Zcpinv Offset EQUATION 20-2: R-C Calculations EQUATION 20-3: R-C Calculations Example EQUATION 20-4: ZCD Event Offset EQUATION 20-5: ZCD Pull-up/down 20.6 Handling Vpeak variations EQUATION 20-6: Series R for V Range 20.7 Operation During Sleep 20.8 Effects of a Reset 20.9 Register Definitions: ZCD Control TABLE 20-1: Register 20-1: ZCDxCON: Zero-Cross Detection Control Register TABLE 20-2: Summary of Registers Associated with the ZCD Module TABLE 20-3: Summary of Configuration Word with the ZCD Module 21.0 Timer0 Module 21.1 Timer0 Operation FIGURE 21-1: Block Diagram of the Timer0 21.2 Register Definitions: Option Register Register 21-1: OPTION_REG: OPTION Register TABLE 21-1: Summary of Registers Associated with Timer0 22.0 Timer1/3/5 Module with Gate Control FIGURE 22-1: Timer1 Block Diagram 22.1 Timer1 Operation TABLE 22-1: Timer1 Enable Selections 22.2 Clock Source Selection TABLE 22-2: Clock Source Selections 22.3 Timer1 Prescaler 22.4 Timer1 (Secondary) Oscillator 22.5 Timer1 Operation in Asynchronous Counter Mode 22.6 Timer1 Gate TABLE 22-3: Timer1 Gate Enable Selections TABLE 22-4: Timer1 Gate Sources 22.7 Timer1 Interrupt 22.8 Timer1 Operation During Sleep 22.9 CCP Capture/Compare Time Base 22.10 CCP Auto-Conversion Trigger FIGURE 22-2: Timer1 Incrementing Edge FIGURE 22-3: Timer1 Gate Enable Mode FIGURE 22-4: Timer1 Gate Toggle Mode FIGURE 22-5: Timer1 Gate Single-Pulse Mode FIGURE 22-6: Timer1 Gate Single-Pulse and Toggle Combined Mode 22.11 Register Definitions: Timer1 Control TABLE 22-5: Register 22-1: T1CON: Timer1 Control Register Register 22-2: T1GCON: Timer1 Gate Control Register TABLE 22-6: Summary of Registers Associated with Timer1 23.0 Timer2/4/6/8 Module FIGURE 23-1: Timer2 Block Diagram FIGURE 23-2: Timer2 Clock Source Block Diagram 23.1 Timer2 Operation 23.2 PRx Period Register 23.3 Timer2 Output 23.4 External Reset Sources TABLE 23-1: Timer2 Operating Modes 23.5 Timer2 Interrupt FIGURE 23-3: Timer2 Prescaler, Postscaler, and Interrupt Timing Diagram 23.6 Operation Examples FIGURE 23-4: Software Gate Mode Timing Diagram (MODE = 00000) FIGURE 23-5: Hardware Gate Mode Timing Diagram (MODE = 00001) FIGURE 23-6: Edge-Triggered Hardware Limit Mode Timing Diagram (MODE = 00100) FIGURE 23-7: Level-Triggered Hardware Limit Mode Timing Diagram (MODE = 00111) FIGURE 23-8: Software Start One-shot Mode Timing Diagram (MODE = 01000) FIGURE 23-9: Edge-Triggered One-Shot Mode Timing Diagram (MODE = 01001) FIGURE 23-10: Edge-Triggered Hardware Limit One-Shot Mode Timing Diagram (MODE = 01100) FIGURE 23-11: Low Level Reset, Edge-Triggered hardware Limit one-Shot Mode Timing Diagram (MODE = 01110) FIGURE 23-12: Rising Edge-Triggered Monostable Mode Timing Diagram (MODE = 10001) FIGURE 23-13: Level-Triggered hardware Limit one-Shot Mode Timing Diagram (MODE = 10110) 23.7 PR2 Period Register 23.8 Timer2 Operation During Sleep 23.9 Register Definitions: Timer2/4/6/8 Control TABLE 23-2: Register 23-1: TxCLKCON: Timerx Clock Selection Register TABLE 23-3: Timerx Clock Sources Register 23-2: TxCON: Timerx Control Register Register 23-3: TxHLT: Timerx Hardware Limit Control Register Register 23-4: TxRST: Timerx External Reset Signal Selection Register TABLE 23-4: External Reset Sources TABLE 23-5: Summary of Registers Associated with Timer2 24.0 Capture/Compare/PWM Modules TABLE 24-1: Available CCP Modules 24.1 Capture Mode FIGURE 24-1: Capture Mode Operation Block Diagram 24.2 Compare Mode FIGURE 24-2: Compare Mode Operation Block Diagram 24.3 PWM Overview FIGURE 24-3: Simplified PWM Block Diagram 24.4 CCP/PWM Clock Selection EQUATION 24-1: PWM Period EQUATION 24-2: Pulse Width EQUATION 24-3: Duty Cycle Ratio FIGURE 24-4: ccpX Duty Cycle Alignment EQUATION 24-4: PWM Resolution TABLE 24-2: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 24-3: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) 24.5 Register Definitions: CCP Control Register 24-1: CCPxCON: CCPx Control Register Register 24-2: CCPTMRS1: PWM Timer Selection Control Register 1 Register 24-3: CCPTMRS2: PWM Timer Selection Control Register 2 Register 24-4: CCPRxL: CCPx Low Byte Register Register 24-5: CCPRxH: CCPx High Byte Register Register 24-6: CCPxCAP: CCPx Capture Input Selection Register 24.6 CCP/PWM Clock Selection 24.7 Register Definitions: CCP/PWM Timers Control Register 24-7: CCPTMRS: PWM Timer Selection Control Register 0 TABLE 24-4: Summary of Registers Associated with Standard PWM 25.0 10-Bit Pulse-Width Modulation (PWM) Module TABLE 25-1: Available 10-bit PWM Modules FIGURE 25-1: Simplified PWM Block Diagram FIGURE 25-2: PWM Output 25.1 PWMx Pin Configuration EQUATION 25-1: PWM Period EQUATION 25-2: Pulse Width EQUATION 25-3: Duty Cycle Ratio EQUATION 25-4: PWM Resolution TABLE 25-2: Example PWM Frequencies and Resolutions (Fosc = 20 MHz) TABLE 25-3: Example PWM Frequencies and Resolutions (Fosc = 8 MHz) 25.2 Register Definitions: 10-Bit PWM Control TABLE 25-4: Register 25-1: PWMxCON: PWM Control Register Register 25-2: PWMXDCH: PWM Duty Cycle High Bits Register 25-3: PWMxDCL: PWM Duty Cycle Low Bits TABLE 25-5: Summary of Registers Associated with 10-bit PWM 26.0 16-bit Pulse-Width Modulation (PWM) Module TABLE 26-1: Available 16-bit PWM Modules FIGURE 26-1: 16-bit PWM Block Diagram FIGURE 26-2: Load Trigger Block Diagram 26.1 Fundamental Operation FIGURE 26-3: PWM Clock Source Block Diagram 26.2 PWM Modes EQUATION 26-1: PWM Period in Standard Mode EQUATION 26-2: PWM Duty Cycle in Standard Mode EQUATION 26-3: PWM Period in Center Aligned Mode EQUATION 26-4: PWM Duty Cycle in Center Aligned Mode FIGURE 26-4: Standard PWM Mode Timing Diagram FIGURE 26-5: Set On Match PWM Mode Timing Diagram FIGURE 26-6: Toggle on Match PWM Mode Timing Diagram FIGURE 26-7: Center Aligned PWM Mode Timing Diagram 26.3 Offset Modes FIGURE 26-8: Independent Run Mode Timing Diagram FIGURE 26-9: Slave Run Mode with Sync Start Timing Diagram FIGURE 26-10: One-Shot Slave Run Mode with Sync Start Timing Diagram FIGURE 26-11: Continuous Slave Run Mode with Immediate Reset and Sync Start Timing Diagram FIGURE 26-12: Offset Match on Incrementing Timer Timing Diagram FIGURE 26-13: Offset Match on Decrementing Timer Timing Diagram 26.4 Reload Operation 26.5 Operation in Sleep Mode 26.6 Interrupts 26.7 Register Definitions: PWM Control TABLE 26-2: Register 26-1: PWMxCON: PWM Control Register Register 26-2: PWMxINTE: PWM Interrupt ENABLE Register Register 26-3: PWMxINTF: PWM Interrupt Request Register Register 26-4: PWMxCLKCON: PWM Clock Control Register Register 26-5: PWMxLDCON: PWM Reload Trigger Source Select Register Register 26-6: PWMxOFCON: PWM Offset Trigger Source Select Register Register 26-7: PWMxPHH: PWMx Phase Count High Register Register 26-8: PWMxPHL: PWMx Phase Count Low Register Register 26-9: PWMxDCH: PWMx Duty Cycle Count High Register Register 26-10: PWMxDCL: PWMx Duty Cycle Count Low Register Register 26-11: PWMxPRH: PWMx Period Count High Register Register 26-12: PWMxPRL: PWMx Period Count Low Register Register 26-13: PWMxOFH: PWMx Offset Count High Register Register 26-14: PWMxOFL: PWMx Offset Count Low Register Register 26-15: PWMxTMRH: PWMx Timer High Register Register 26-16: PWMxTMRL: PWMx Timer Low Register Register 26-17: PWMEN: PWMEN Bit Mirror Register Register 26-18: PWMLD: LDA Bit Mirror Register Register 26-19: PWMOUT: PWMOUT Bit Mirror Register TABLE 26-3: Summary of Registers Associated with PWM TABLE 26-4: Summary of Configuration Words with Clock Sources 27.0 Complementary Output Generator (COG) Modules TABLE 27-1: Available cog Modules 27.1 Output to Pins (all modes) 27.2 Event-Driven PWM (All Modes) 27.3 Modes of Operation FIGURE 27-1: Example of Full-Bridge Application FIGURE 27-2: Simplified COG Block Diagram (Steered PWM Mode, MD = 0) FIGURE 27-3: Simplified COG Block Diagram (Synchronous Steered PWM Mode, MD = 1) FIGURE 27-4: Simplified COG Block Diagram (Full-Bridge Modes, Forward: MD = 2, Reverse: MD = 3) FIGURE 27-5: Simplified COG Block Diagram (Half-Bridge Mode, MD = 4) FIGURE 27-6: Simplified COG Block Diagram (Push-Pull Mode, MD = 5) FIGURE 27-7: COG (Rising/Falling) Input Block FIGURE 27-8: COG (Rising/Falling) Dead-Band Block FIGURE 27-9: Typical Half-Bridge Mode COG Operation with CCP1 FIGURE 27-10: Half-Bridge Mode COG Operation with CCP1 and Phase Delay FIGURE 27-11: Push-Pull Mode COG Operation with CCP1 FIGURE 27-12: Full-Bridge Forward Mode COG Operation with CCP1 FIGURE 27-13: Full-Bridge Mode COG Operation with CCP1 and Direction Change 27.4 Clock Sources 27.5 Selectable Event Sources FIGURE 27-14: Edge Vs. Level Sense 27.6 Output Control TABLE 27-2: Pin Output States MD<2:0> = 00x TABLE 27-3: Pin Output States MD<2:0> > 001 27.7 Dead-Band Control 27.8 Blanking Control 27.9 Phase Delay EQUATION 27-1: Phase, Dead-Band, and Blanking Time Calculation EXAMPLE 27-1: Timer Uncertainty 27.10 Auto-Shutdown Control FIGURE 27-15: Auto-Shutdown Waveform – CCP1 as Rising and Falling Event Input Source 27.11 Buffer Updates 27.12 Input and Output Pin Selection 27.13 Operation During Sleep 27.14 Configuring the COG 27.15 Register Definitions: COG Control TABLE 27-4: Register 27-1: COGxCON0: COG Control Register 0 Register 27-2: COGxCON1: COG Control Register 1 Register 27-3: COGxRIS0: COG Rising Event Input Selection Register Register 27-4: COGxRIS1: COG Rising Event Input Selection Register TABLE 27-5: Rising/Falling Event Input Sources Register 27-5: COGxRSIM0: COG Rising Event Source Input Mode Register Register 27-6: COGxRSIM1: COG Rising Event Source Input Mode Register Register 27-7: COGxFIS0: COG Falling Event Input Selection Register Register 27-8: COGxFIS1: COG Falling Event Input Selection Register Register 27-9: COGxFSIM0: COG Falling Event Source Input Mode Register Register 27-10: COGxFSIM1: COG Falling Event Source Input Mode Register Register 27-11: COGXASD0: COG Auto-Shutdown Control Register 0 Register 27-12: COGXASD1: COG Auto-Shutdown Control Register 1 TABLE 27-6: Auto-Shutdown Sources Register 27-13: COGXSTR: COG Steering Control Register 1(1) Register 27-14: COGXDBR: COG Rising Event Dead-Band Count Register Register 27-15: COGXDBF: COG Falling Event Dead-Band Count Register Register 27-16: COGXBLKR: COG Rising Event Blanking Count Register Register 27-17: COGXBLKF: COG Falling Event Blanking Count Register Register 27-18: COGXPHR: COG Rising Event Phase Delay Count Register Register 27-19: COGXPHF: COG Falling Event Phase Delay Count Register TABLE 27-7: Summary of Registers Associated with COGx 28.0 Configurable Logic Cell (CLC) FIGURE 28-1: CLCx Simplified Block Diagram 28.1 CLCx Setup TABLE 28-1: CLCx Data Input Selection TABLE 28-2: Data Gating Logic 28.2 CLCx Interrupts 28.3 Output Mirror Copies 28.4 Effects of a Reset 28.5 Operation During Sleep FIGURE 28-2: Input Data Selection and Gating FIGURE 28-3: Programmable Logic Functions 28.6 Register Definitions: CLC Control TABLE 28-3: Register 28-1: CLCxCON: Configurable Logic Cell Control Register Register 28-2: CLCxPOL: Signal Polarity Control Register Register 28-3: CLCxSEL0: Generic CLCx Data 1 Select Register Register 28-4: CLCxSEL1: Generic CLCx Data 2 Select Register Register 28-5: CLCxSEL2: Generic CLCx Data 3 Select Register Register 28-6: CLCxSEL3: Generic CLCx Data 4 Select Register Register 28-7: CLCxGLS0: Gate 1 Logic Select Register Register 28-8: CLCxGLS1: Gate 2 Logic Select Register Register 28-9: CLCxGLS2: Gate 3 Logic Select Register Register 28-10: CLCxGLS3: Gate 4 Logic Select Register Register 28-11: CLCDATA: CLC Data Output TABLE 28-4: Summary of Registers Associated with CLCx 29.0 Operational Amplifier (OPA) Modules FIGURE 29-1: OPAx Module Block Diagram 29.1 OPA Module Performance 29.2 OPA Module Control 29.3 Override Control 29.4 Effects of Reset 29.5 Effects of Sleep 29.6 Register Definitions: Op Amp Control TABLE 29-1: Register 29-1: OPAxCON: Operational Amplifier (OPAx) Control Register Register 29-2: OPAxORS: Op Amp Override Source Selection Register TABLE 29-2: Override Sources Register 29-3: OPAxNCHS: Op Amp Negative Channel Source Select Register TABLE 29-3: Inverting Input Sources Register 29-4: OPAxPCHS: Op Amp Positive Channel Source Select Register TABLE 29-4: Non-Inverting Input Sources TABLE 29-5: Summary of Registers Associated with Op Amps 30.0 Programmable Ramp Generator (PRG) Module 30.1 Fundamental Operation 30.2 Enable, Ready, Go 30.3 Independent Set_rising and Set_falling Timing Inputs 30.4 Level and Edge Timing Sensitivity 30.5 One-Shot Minimum Timing 30.6 DAC Voltage Sources 30.7 Operation During Sleep 30.8 Effects of a Reset FIGURE 30-1: Simplified PRG Module Block Diagram FIGURE 30-2: Slope Compensation (Falling ramp) Timing Diagram (MODE = 00) FIGURE 30-3: Alternating Rising/Falling Ramp Generation Timing Diagram (OS = 0, MODE = 01) FIGURE 30-4: Alternating Rising/Falling Ramp Generation Timing Diagram (OS = 1, MODE = 01) FIGURE 30-5: Rising Ramp Generation Timing Diagram (MODE = 10) 30.9 Slope Compensation Application EQUATION 30-1: EQUATION 30-2: FIGURE 30-6: Example Slope Compensation Circuit 30.10 Register Definitions: Slope Compensation Control TABLE 30-1: Register 30-1: PRGxCON0: Programmable Ramp Generator Control 0 Register Register 30-2: PRGxCON1: Programmable Ramp Generator Control 1 Register Register 30-3: PRGxINS: Voltage Input Select Register TABLE 30-2: Voltage Input Sources Register 30-4: PRGxCON2: Programmable Ramp Generator Control 2 Register TABLE 30-3: Programmable Ramp Generator Current Settings Register 30-5: PRGxRTSS: Set_rising Timing Source Select Register Register 30-6: PRGxFTSS: Set_falling Timing Source Select Register TABLE 30-4: Programmable Ramp Generator Timing Sources TABLE 30-5: Summary of Registers Associated with the pRG Module 31.0 Data Signal Modulator (DSM) FIGURE 31-1: Simplified Block Diagram of the Data Signal Modulator 31.1 DSM Operation 31.2 Modulator Signal Sources 31.3 Carrier Signal Sources 31.4 Carrier Synchronization FIGURE 31-2: On OFF Keying (OOK) Synchronization FIGURE 31-3: No SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 0) FIGURE 31-4: Carrier High SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 0) FIGURE 31-5: Carrier Low SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 1) FIGURE 31-6: Full Synchronization (MDCHSYNC = 1, MDCLSYNC = 1) 31.5 Input and Output Through Pins TABLE 31-1: 31.6 Carrier Source Polarity Select 31.7 Programmable Modulator Data 31.8 Modulated Output Polarity 31.9 Operation in Sleep Mode 31.10 Effects of a Reset 31.11 Register Definitions: Data Signal Modulator TABLE 31-2: Register 31-1: MDxCON0: Modulation Control Register 0 Register 31-2: MDxCON1: Modulation Control Register 1 Register 31-3: MDxSRC: Modulation Source Control Register TABLE 31-3: Modulation Source Register 31-4: MDxCARH: Modulation High Carrier Control Register TABLE 31-4: High Carrier Source Register 31-5: MDxCARL: Modulation Low Carrier Control Register TABLE 31-5: Low Carrier Source TABLE 31-6: Summary of Registers Associated with Data Signal Modulator Mode 32.0 Master Synchronous Serial Port (MSSP) Module 32.1 MSSP Module Overview FIGURE 32-1: MSSP Block Diagram (SPI Mode) FIGURE 32-2: MSSP Block Diagram (I2C Master Mode) FIGURE 32-3: MSSP Block Diagram (I2C Slave Mode) 32.2 SPI Mode Overview FIGURE 32-4: SPI Master and Multiple Slave Connection FIGURE 32-5: SPI Master/Slave Connection FIGURE 32-6: SPI Mode Waveform (Master Mode) FIGURE 32-7: SPI Daisy-Chain Connection FIGURE 32-8: Slave Select Synchronous Waveform FIGURE 32-9: SPI Mode Waveform (Slave Mode with CKE = 0) FIGURE 32-10: SPI Mode Waveform (Slave Mode with CKE = 1) TABLE 32-1: Summary of Registers Associated with SPI Operation 32.3 I2C Mode Overview FIGURE 32-11: I2C Master/ Slave Connection 32.4 I2C Mode Operation TABLE 32-2: I2C Bus Terms FIGURE 32-12: I2C Start and Stop Conditions FIGURE 32-13: I2C Restart Condition 32.5 I2C Slave Mode Operation FIGURE 32-14: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 32-15: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 32-16: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1) FIGURE 32-17: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1) FIGURE 32-18: I2C Slave, 7-bit Address, Transmission (AHEN = 0) FIGURE 32-19: I2C Slave, 7-bit Address, Transmission (AHEN = 1) FIGURE 32-20: I2C Slave, 10-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 32-21: I2C Slave, 10-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 32-22: I2C Slave, 10-bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 32-23: Clock Synchronization Timing FIGURE 32-24: Slave Mode General Call Address Sequence 32.6 I2C Master Mode FIGURE 32-25: Baud Rate Generator Timing with Clock Arbitration FIGURE 32-26: First Start Bit Timing FIGURE 32-27: Repeated Start Condition Waveform FIGURE 32-28: I2C Master Mode Waveform (Transmission, 7 or 10-bit Address) FIGURE 32-29: I2C Master Mode Waveform (Reception, 7-bit Address) FIGURE 32-30: Acknowledge Sequence Waveform FIGURE 32-31: Stop Condition Receive or Transmit Mode FIGURE 32-32: Bus Collision Timing for Transmit and Acknowledge FIGURE 32-33: Bus Collision During Start Condition (SDA Only) FIGURE 32-34: Bus Collision During Start Condition (SCL = 0) FIGURE 32-35: BRG Reset Due to SDA Arbitration During Start Condition FIGURE 32-36: Bus Collision During a Repeated Start Condition (Case 1) FIGURE 32-37: Bus Collision During Repeated Start Condition (Case 2) FIGURE 32-38: Bus Collision During a Stop Condition (Case 1) FIGURE 32-39: Bus Collision During a Stop Condition (Case 2) TABLE 32-3: Summary of Registers Associated with I2C Operation 32.7 Baud Rate Generator FIGURE 32-40: Baud Rate Generator Block Diagram TABLE 32-4: MSSP Clock Rate w/BRG 32.8 Register Definitions: MSSP Control Register 32-1: SSP1STAT: SSP STATUS Register Register 32-2: SSP1CON1: SSP Control Register 1 Register 32-3: SSP1CON2: SSP Control Register 2(1) Register 32-4: SSP1CON3: SSP Control Register 3 Register 32-5: SSP1MSK: SSP Mask Register Register 32-6: SSP1ADD: MSSP Address and Baud Rate Register (I2C Mode) 33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) FIGURE 33-1: EUSART Transmit Block Diagram FIGURE 33-2: EUSART Receive Block Diagram 33.1 EUSART Asynchronous Mode FIGURE 33-3: Asynchronous Transmission FIGURE 33-4: Asynchronous Transmission (Back-to-Back) TABLE 33-1: Summary of Registers Associated with Asynchronous Transmission FIGURE 33-5: Asynchronous Reception TABLE 33-2: Summary of Registers Associated with Asynchronous Reception 33.2 Clock Accuracy with Asynchronous Operation 33.3 Register Definitions: EUSART Control Register 33-1: TX1STA: Transmit Status and Control Register Register 33-2: RC1STA: Receive Status and Control Register Register 33-3: BAUD1CON: Baud Rate Control Register 33.4 EUSART Baud Rate Generator (BRG) EXAMPLE 33-1: Calculating Baud Rate Error TABLE 33-3: Baud Rate Formulas TABLE 33-4: Summary of Registers Associated with the Baud Rate Generator TABLE 33-5: BAUD Rates for Asynchronous Modes TABLE 33-6: BRG Counter Clock Rates FIGURE 33-6: Automatic Baud Rate Calibration(1) FIGURE 33-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation FIGURE 33-8: Auto-Wake-up Bit (WUE) Timings During Sleep FIGURE 33-9: Send Break Character Sequence 33.5 EUSART Synchronous Mode FIGURE 33-10: Synchronous Transmission FIGURE 33-11: Synchronous Transmission (Through TXEN) TABLE 33-7: Summary of Registers Associated with Synchronous Master Transmission FIGURE 33-12: Synchronous Reception (Master Mode, SREN) TABLE 33-8: Summary of Registers Associated with Synchronous Master Reception TABLE 33-9: Summary of Registers Associated with Synchronous Slave Transmission TABLE 33-10: Summary of Registers Associated with Synchronous Slave Reception 33.6 EUSART Operation During Sleep 34.0 In-Circuit Serial Programming™ (ICSP™) 34.1 High-Voltage Programming Entry Mode 34.2 Low-Voltage Programming Entry Mode 34.3 Common Programming Interfaces FIGURE 34-1: ICD RJ-11 Style Connector Interface FIGURE 34-2: PICkit™ Programmer Style Connector Interface FIGURE 34-3: Typical Connection for ICSP™ Programming 35.0 Instruction Set Summary 35.1 Read-Modify-Write Operations TABLE 35-1: Opcode Field Descriptions TABLE 35-2: Abbreviation Descriptions FIGURE 35-1: General Format for Instructions TABLE 35-3: PIC16(L)F1773/6 Instruction Set TABLE 35-3: PIC16(L)F1773/6 Instruction Set (Continued) 35.2 Instruction Descriptions 36.0 Electrical Specifications 36.1 Absolute Maximum Ratings(†) 36.2 Standard Operating Conditions FIGURE 36-1: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16F1773/6 Only FIGURE 36-2: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16LF1773/6 Only 36.3 DC Characteristics TABLE 36-1: Supply Voltage FIGURE 36-3: POR and POR Rearm with Slow Rising Vdd TABLE 36-2: Supply Current (Idd)(1,2) TABLE 36-3: Power-Down Currents (Ipd)(1,2) TABLE 36-4: I/O Ports TABLE 36-5: Memory Programming Specifications TABLE 36-6: Thermal Characteristics 36.4 AC Characteristics FIGURE 36-4: Load Conditions FIGURE 36-5: Clock Timing TABLE 36-7: Clock Oscillator Timing Requirements TABLE 36-8: Oscillator Parameters FIGURE 36-6: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature TABLE 36-9: PLL Clock Timing Specifications FIGURE 36-7: CLKOUT and I/O Timing TABLE 36-10: CLKOUT and I/O Timing Parameters FIGURE 36-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing TABLE 36-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters FIGURE 36-9: Timer0 and Timer1 External Clock Timings FIGURE 36-10: Brown-Out Reset Timing and Characteristics TABLE 36-12: Timer0 and Timer1 External Clock Requirements FIGURE 36-11: Capture/Compare/PWM Timings (CCP) TABLE 36-13: Capture/Compare/PWM Requirements (CCP) FIGURE 36-12: CLC Propagation Timing TABLE 36-14: Configuration Logic Cell (CLC) Characteristics TABLE 36-15: Analog-to-Digital Converter (ADC) Characteristics(1,2,3,4): TABLE 36-16: ADC Conversion Requirements FIGURE 36-13: ADC Conversion Timing (ADC Clock Fosc-based) FIGURE 36-14: ADC Conversion Timing (ADC Clock from FRC) TABLE 36-17: Operational Amplifier (OPA) TABLE 36-18: Programmable Ramp Generator (PRG) Specifications TABLE 36-19: Comparator Specifications TABLE 36-20: 10-bit Digital-to-Analog Converter (DAC) Specifications TABLE 36-21: 5-bit Digital-to-Analog Converter (DAC) Specifications TABLE 36-22: Zero Cross Pin Specifications FIGURE 36-15: EUSART Synchronous Transmission (Master/Slave) Timing TABLE 36-23: EUSART Synchronous Transmission Requirements FIGURE 36-16: eUSART Synchronous Receive (Master/Slave) Timing TABLE 36-24: eUSART Synchronous Receive Requirements FIGURE 36-17: SPI Master Mode Timing (CKE = 0, SMP = 0) FIGURE 36-18: SPI Master Mode Timing (CKE = 1, SMP = 1) FIGURE 36-19: SPI Slave Mode Timing (CKE = 0) FIGURE 36-20: SPI Slave Mode Timing (CKE = 1) TABLE 36-25: SPI Mode Requirements FIGURE 36-21: I2C Bus Start/Stop Bits Timing TABLE 36-26: I2C Bus Start/Stop Bits Requirements FIGURE 36-22: I2C Bus Data Timing TABLE 36-27: I2C Bus Data Requirements 37.0 DC and AC Characteristics Graphs and Charts 38.0 Development Support 38.1 MPLAB X Integrated Development Environment Software 38.2 MPLAB XC Compilers 38.3 MPASM Assembler 38.4 MPLINK Object Linker/ MPLIB Object Librarian 38.5 MPLAB Assembler, Linker and Librarian for Various Device Families 38.6 MPLAB X SIM Software Simulator 38.7 MPLAB REAL ICE In-Circuit Emulator System 38.8 MPLAB ICD 3 In-Circuit Debugger System 38.9 PICkit 3 In-Circuit Debugger/ Programmer 38.10 MPLAB PM3 Device Programmer 38.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 38.12 Third-Party Development Tools 39.0 Packaging Information 39.1 Package Marking Information Package Marking Information (Continued) 39.2 Package Details Appendix A: Data Sheet Revision History Revision A (09/2015) Revision B (10/2016) The Microchip Website Customer Change Notification Service Customer Support Product Identification System Trademarks Worldwide Sales