Datasheet MCP41XXX/42XXX (Microchip) - 5

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MCP41XXX/42XXX Absolute Maximum Ratings †
VDD...7.0V
† Notice:
Stresses above those listed under “maximum rat- All inputs and outputs w.r.t. V ings” may cause permanent damage to the device. This is a SS ... -0.6V to VDD +1.0V stress rating only and functional operation of the device at Storage temperature ...-60°C to +150°C those or any other conditions above those indicated in the Ambient temp. with power applied ..-60°C to +125°C operational listings of this specification is not implied. Expo- ESD protection on all pins ..≥ 2 kV sure to maximum rating conditions for extended periods may affect device reliability.
AC TIMING CHARACTERISTICS Electrical Characteristics:
Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C.
Parameter Sym Min. Typ. Max. Units Conditions
Clock Frequency FCLK — — 10 MHz VDD = 5V
(Note 1)
Clock High Time tHI 40 — — ns Clock Low Time tLO 40 — — ns CS Fall to First Rising CLK Edge tCSSR 40 — — ns Data Input Setup Time tSU 40 — — ns Data Input Hold Time tHD 10 — — ns SCK Fall to SO Valid Propagation Delay tDO — 80 ns CL = 30 pF
(Note 2)
SCK Rise to CS Rise Hold Time tCHS 30 — — ns SCK Rise to CS Fall Delay tCS0 10 — — ns CS Rise to CLK Rise Hold tCS1 100 — — ns CS High Time tCSH 40 — — ns Reset Pulse Width tRS 150 — — ns
Note 2
RS Rising to CS Falling Delay Time tRSCS 150 — — ns
Note 2
CS rising to RS or SHDN falling delay time tSE 40 — — ns
Note 3
CS low time tCSL 100 — — ns
Note 3
Shutdown Pulse Width tSH 150 — — ns
Note 3 Note 1:
When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of propagation delay time (tDO) and data input setup time (tSU). Max. clock frequency is therefore ~ 5.8 MHz based on SCK rise and fall times of 5 ns, tHI = 40 ns, tDO = 80 ns and tSU = 40 ns.
2:
Applies only to the MCP42XXX devices.
3:
Applies only when using hardware pins to exit software shutdown mode, MCP42XXX only. 2003 Microchip Technology Inc. DS11195C-page 5 Document Outline 1.0 Electrical Characteristics Figure 1-1: Detailed Serial interface Timing. Figure 1-2: Reset Timing. Figure 1-3: Software Shutdown Exit Timing. 2.0 Typical Performance Curves Figure 2-1: Normalized Wiper to End Terminal Resistance vs. Code. Figure 2-2: Potentiometer INL Error vs. Code. Figure 2-3: Potentiometer Mode Tempco vs. Code. Figure 2-4: Nominal Resistance 10kW vs. Temperature. Figure 2-5: Nominal Resistance 50kW vs. Temperature. Figure 2-6: Nominal Resistance 100kW vs. Temperature. Figure 2-7: Rheostat INL Error vs. Code. Figure 2-8: Rheostat Mode Tempco vs. Code. Figure 2-9: Static Current vs. Temperature. Figure 2-10: Active Supply Current vs. Temperature. Figure 2-11: Active Supply Current vs. Clock Frequency. Figure 2-12: Reset & Shutdown Pins Current vs. Voltage. Figure 2-13: 10kW Device Wiper Resistance Histogram. Figure 2-14: 50kW, 100kW Device Wiper Resistance Histogram. Figure 2-15: One Position Settling Time. Figure 2-16: Full-Scale Settling Time. Figure 2-17: Digital Feed through vs. Time. Figure 2-18: Gain vs. Frequency for 10kW Potentiometer. Figure 2-19: Gain vs. Frequency for 50kW Potentiometer. Figure 2-20: Gain vs. Frequency for 100kW Potentiometer. Figure 2-21: -3 dB Bandwidths. Figure 2-22: Power Supply Rejection Ratio vs. Frequency. Figure 2-23: 10kW Wiper Resistance vs. Voltage. Figure 2-24: 50kW & 100kW Wiper Resistance vs. Voltage. 2.1 Parametric Test Circuits Figure 2-25: Potentiometer Divider Non- Linearity Error Test Circuit (DNL, INL). Figure 2-26: Resistor Position Non- Linearity Error Test Circuit (Rheostat operation DNL, INL). Figure 2-27: Wiper Resistance Test Circuit. Figure 2-28: Power Supply Sensitivity Test Circuit (PSS, PSRR). Figure 2-29: Gain vs. Frequency Test Circuit. Figure 2-30: Capacitance Test Circuit. 3.0 Pin Descriptions 3.1 PA0, PA1 3.2 PB0, PB1 3.3 PW0, PW1 3.4 Chip Select (CS) 3.5 Serial Clock (SCK) 3.6 Serial Data Input (SI) 3.7 Serial Data Output (SO) (MCP42XXX devices only) 3.8 Reset (RS) (MCP42XXX devices only) 3.9 Shutdown (SHDN) (MCP42XXX devices only) Table 3-1: MCP41XXX Pins Table 3-2: MCP42XXX Pins 4.0 Applications Information Figure 4-1: Block diagram showing the MCP42XXX dual digital potentiometer. Data register 0 and da... 4.1 Modes of Operation Figure 4-2: Two-terminal or rheostat configuration for the digital potentiometer. Acting as a res... Figure 4-3: Three terminal or voltage divider mode. 4.2 Typical Applications Figure 4-4: Single-supply, programmable, inverting gain amplifier using a digital potentiometer. Figure 4-5: Single-supply, programmable, non-inverting gain amplifier. Figure 4-6: Gain vs. Code for inverting and differential amplifier circuits. Figure 4-7: Single Supply programmable differential amplifier using digital potentiometers. Figure 4-8: By changing the values of R1 and R2, the voltage output resolution of this programmab... 4.3 Calculating Resistances Figure 4-9: Potentiometer resistances are a function of code. It should be noted that, when using... Figure 4-10: Example Resistance calculations. 5.0 Serial Interface 5.1 Command Byte 5.2 Writing Data Into Data Registers 5.3 Using The Shutdown Command Figure 5-1: Timing Diagram for Writing Instructions or Data to a Digital Potentiometer. Figure 5-2: Command Byte Format. 5.4 Daisy-Chain Configuration Figure 5-3: Timing Diagram for Daisy-Chain Configuration. Figure 5-4: Daisy-Chain Configuration. 5.5 Reset (RS) Pin Operation 5.6 Shutdown (SHDN) Pin Operation 5.7 Power-up Considerations Table 5-1: Truth Table for Logic Inputs 5.8 Using the MCP41XXX/42XXX in SPI Mode 1,1 Figure 5-5: Timing Diagram for SPI Mode 1,1 Operation. 6.0 Packaging Information 6.1 Package Marking Information