Datasheet VP0550 (Supertex)
| Manufacturer | Supertex |
| Description | P-Channel Enhancement-Mode Vertical DMOS FETs |
| Pages / Page | 5 / 1 — Supertex inc. VP0550. P-Channel Enhancement-Mode. Vertical DMOS FETs. … |
| Revision | 06-27-2014 |
| File Format / Size | PDF / 641 Kb |
| Document Language | English |
Supertex inc. VP0550. P-Channel Enhancement-Mode. Vertical DMOS FETs. Features. General Description. Applications
Model Line for this Datasheet
Text Version of Document
Supertex inc. VP0550 P-Channel Enhancement-Mode Vertical DMOS FETs Features General Description
► Free from secondary breakdown This enhancement-mode (normally-off) transistor utilizes ► Low power drive requirement a vertical DMOS structure and Supertex’s well-proven, ► Ease of paralleling silicon-gate manufacturing process. This combination ► Low C and fast switching speeds produces a device with the power handling capabilities ISS of bipolar transistors and the high input impedance and ► Excellent thermal stability positive temperature coefficient inherent in MOS devices. ► Integral source-drain diode Characteristic of all MOS structures, this device is free ► High input impedance and high gain from thermal runaway and thermally-induced secondary
Applications
breakdown. ► Motor controls Supertex’s vertical DMOS FETs are ideally suited to a ► Converters wide range of switching and amplifying applications where ► Amplifiers very low threshold voltage, high breakdown voltage, high ► Switches input impedance, low input capacitance, and fast switching ► Power supply circuits speeds are desired. ► Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.)
Ordering Information Product Summary Part Number Package Option Packing R I BV /BV DS(ON) D(ON) DSS DGS
VP0550N3-G TO-92 1000/Bag
(max) (min)
VP0550N3-G P002 -500V 125Ω -100mA VP0550N3-G P003 VP0550N3-G P005 TO-92 2000/Reel
Pin Configuration
VP0550N3-G P013 VP0550N3-G P014 -G denotes a lead (Pb)-free / RoHS compliant package. Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
DRAIN Absolute Maximum Ratings SOURCE Parameter Value GATE
Drain-to-source voltage BVDSS
TO-92
Drain-to-gate voltage BVDGS Gate-to-source voltage ±20V
Product Marking
Operating and storage temperature -55OC to +150OC
SiVP
YY = Year Sealed Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation
0 5 5 0
WW = Week Sealed of the device at the absolute rating level may affect device reliability. All voltages are
Y Y W W
= “Green” Packaging referenced to device ground. Package may or may not include the following marks: Si or
Typical Thermal Resistance TO-92 Package θja
TO-92 132OC/W Doc.# DSFP-VP0550
Supertex inc.
C082313
www.supertex.com
► Free from secondary breakdown This enhancement-mode (normally-off) transistor utilizes ► Low power drive requirement a vertical DMOS structure and Supertex’s well-proven, ► Ease of paralleling silicon-gate manufacturing process. This combination ► Low C and fast switching speeds produces a device with the power handling capabilities ISS of bipolar transistors and the high input impedance and ► Excellent thermal stability positive temperature coefficient inherent in MOS devices. ► Integral source-drain diode Characteristic of all MOS structures, this device is free ► High input impedance and high gain from thermal runaway and thermally-induced secondary
Applications
breakdown. ► Motor controls Supertex’s vertical DMOS FETs are ideally suited to a ► Converters wide range of switching and amplifying applications where ► Amplifiers very low threshold voltage, high breakdown voltage, high ► Switches input impedance, low input capacitance, and fast switching ► Power supply circuits speeds are desired. ► Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.)
Ordering Information Product Summary Part Number Package Option Packing R I BV /BV DS(ON) D(ON) DSS DGS
VP0550N3-G TO-92 1000/Bag
(max) (min)
VP0550N3-G P002 -500V 125Ω -100mA VP0550N3-G P003 VP0550N3-G P005 TO-92 2000/Reel
Pin Configuration
VP0550N3-G P013 VP0550N3-G P014 -G denotes a lead (Pb)-free / RoHS compliant package. Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
DRAIN Absolute Maximum Ratings SOURCE Parameter Value GATE
Drain-to-source voltage BVDSS
TO-92
Drain-to-gate voltage BVDGS Gate-to-source voltage ±20V
Product Marking
Operating and storage temperature -55OC to +150OC
SiVP
YY = Year Sealed Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation
0 5 5 0
WW = Week Sealed of the device at the absolute rating level may affect device reliability. All voltages are
Y Y W W
= “Green” Packaging referenced to device ground. Package may or may not include the following marks: Si or
Typical Thermal Resistance TO-92 Package θja
TO-92 132OC/W Doc.# DSFP-VP0550
Supertex inc.
C082313
www.supertex.com
