Datasheet LTC4300A-1, LTC4300A-2 (Analog Devices) - 8

LTC4300A-1/LTC4300A-2
OPERATION Start-Up
Another key feature of the connection circuitry is that it provides bidirectional buffering, keeping the backplane When the LTC4300A first receives power on its VCC pin, and card capacitances isolated. Because of this isolation, either during power-up or during live insertion, it starts the waveforms on the backplane busses look slightly in an undervoltage lockout (UVLO) state, ignoring any different than the corresponding card bus waveforms, as activity on the SDA and SCL pins until VCC rises above described here. 2.5V. For the LTC4300A-2, the part also waits for VCC2 to rise above 2V. This ensures that the part does not try to
Input to Output Offset Voltage
function until it has enough voltage to do so. When a logic low voltage, VLOW1, is driven on any of the During this time, the 1V precharge circuitry is also ac- LTC4300A’s data or clock pins, the LTC4300A regulates tive and forces 1V through 100k nominal resistors to the the voltage on the other side of the chip (call it VLOW2) SDA and SCL pins. Because the I/O card is being plugged to a slightly higher voltage, as directed by the following into a live backplane, the voltage on the backplane SDA equation: and SCL busses may be anywhere between 0V and VCC. Precharging the SCL and SDA pins to 1V minimizes the VLOW2 = VLOW1 + 75mV + (VCC/R) • 100 worst-case voltage differential these pins will see at the where R is the bus pull-up resistance in ohms. For ex- moment of connection, therefore minimizing the amount ample, if a device is forcing SDAOUT to 10mV where of disturbance caused by the I/O card. VCC = 3.3V and the pull-up resistor R on SDAIN is 10k, Once the LTC4300A comes out of UVLO, it assumes that then the voltage on SDAIN = 10mV + 75mV + (3.3/10000) SDAIN and SCLIN have been inserted into a live system • 100 = 118mV. See the Typical Performance Character- and that SDAOUT and SCLOUT are being powered up at the istics section for curves showing the offset voltage as a same time as itself. Therefore, it looks for either a stop bit function of VCC and R. or bus idle condition on the backplane side to indicate the
Propagation Delays
completion of a data transaction. When either one occurs, the part also verifies that both the SDAOUT and SCLOUT During a rising edge, the rise-time on each side is deter- voltages are high. When all of these conditions are met, mined by the combined pull-up current of the LTC4300A the input-to-output connection circuitry is activated, joining boost current and the bus resistor and the equivalent the SDA and SCL busses on the I/O card with those on capacitance on the line. If the pull-up currents are the the backplane, and the rise time accelerators are enabled. same, a difference in rise-time occurs which is directly proportional to the difference in capacitance between the
Connection Circuitry
two sides. This effect is displayed in Figure 1 for VCC = Once the connection circuitry is activated, the functionality 3.3V and a 10k pull-up resistor on each side (50pF on of the SDAIN and SDAOUT pins is identical. A low forced on one side and 150pF on the other). Since the output side either pin at any time results in both pin voltages being low. has less capacitance than the input, it rises faster and the For proper operation, logic low input voltages should be effective tPLH is negative. no higher than 0.4V with respect to the ground pin voltage There is a finite propagation delay, tPHL, through the con- of the LTC4300A. SDAIN and SDAOUT enter a logic high nection circuitry for falling waveforms. Figure 2 shows state only when all devices on both SDAIN and SDAOUT the falling edge waveforms for the same VCC, pull-up release high. The same is true for SCLIN and SCLOUT. resistors and equivalent capacitance conditions as used This important feature ensures that clock stretching, clock in Figure 1. An external NMOS device pulls down the volt- synchronization, arbitration and the acknowledge protocol age on the side with 150pF capacitance; the LTC4300A always work, regardless of how the devices in the system pulls down the voltage on the opposite side, with a delay are tied to the LTC4300A. of 55ns. This delay is always positive and is a function of 4300a12fa 8