Datasheet LTC4301 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Supply Independent Hot Swappable 2-Wire Bus Buffer |
| Pages / Page | 12 / 6 — OPERATIO. Ready Digital Output. Connection Sense. Figure 2. Input-Output … |
| File Format / Size | PDF / 229 Kb |
| Document Language | English |
OPERATIO. Ready Digital Output. Connection Sense. Figure 2. Input-Output Connection. High to Low Propagation Delay
Model Line for this Datasheet
Text Version of Document
LTC4301
U OPERATIO
There is a finite high to low propagation delay through the
Ready Digital Output
connection circuitry for falling waveforms. Figure 2 shows This pin provides a digital flag which is low when either CS the falling edge waveforms for the same pull-up resistors is high or the start-up sequence described earlier in this and equivalent capacitance conditions as used in Figure 1. section has not been completed. READY goes high when An external N-channel MOSFET device pulls down the CS is low and start-up is complete. The pin is driven by an voltage on the side with 55pF capacitance; LTC4301 pulls open-drain pull-down capable of sinking 3mA while hold- down the voltage on the opposite side with a delay of 60ns. ing 0.4V on the pin. Connect a resistor of 10k to V This delay is always positive and is a function of supply CC to provide the pull-up. voltage, temperature and the pull-up resistors and equiva- lent bus capacitances on both sides of the bus. The Typical
Connection Sense
Performance Characteristics section shows high to low propagation delay as a function of temperature and volt- When the CS pin is driven above 1.4V with respect to the age for 10k pull-up resistors pulled-up to V LTC4301’s ground, the backplane side is disconnected CC and 100pF equivalent capacitance on both sides of the part. Larger from the card side and the READY pin is internally pulled output capacitances translate to longer delays (up to low. When the pin voltage is low, the part waits for data 150ns). Users must quantify the difference in propagation transactions on both the backplane and card sides to be times for a rising edge versus a falling edge in their complete (as described in the Start-Up section) before systems and adjust setup and hold times accordingly. reconnecting the two sides. At this time the internal pulldown on READY releases. INPUT OUTPUT SIDE SIDE 55pF 20pF 1V/DIV 4301 F02 20ns/DIV
Figure 2. Input-Output Connection High to Low Propagation Delay
4301fb 6
U OPERATIO
There is a finite high to low propagation delay through the
Ready Digital Output
connection circuitry for falling waveforms. Figure 2 shows This pin provides a digital flag which is low when either CS the falling edge waveforms for the same pull-up resistors is high or the start-up sequence described earlier in this and equivalent capacitance conditions as used in Figure 1. section has not been completed. READY goes high when An external N-channel MOSFET device pulls down the CS is low and start-up is complete. The pin is driven by an voltage on the side with 55pF capacitance; LTC4301 pulls open-drain pull-down capable of sinking 3mA while hold- down the voltage on the opposite side with a delay of 60ns. ing 0.4V on the pin. Connect a resistor of 10k to V This delay is always positive and is a function of supply CC to provide the pull-up. voltage, temperature and the pull-up resistors and equiva- lent bus capacitances on both sides of the bus. The Typical
Connection Sense
Performance Characteristics section shows high to low propagation delay as a function of temperature and volt- When the CS pin is driven above 1.4V with respect to the age for 10k pull-up resistors pulled-up to V LTC4301’s ground, the backplane side is disconnected CC and 100pF equivalent capacitance on both sides of the part. Larger from the card side and the READY pin is internally pulled output capacitances translate to longer delays (up to low. When the pin voltage is low, the part waits for data 150ns). Users must quantify the difference in propagation transactions on both the backplane and card sides to be times for a rising edge versus a falling edge in their complete (as described in the Start-Up section) before systems and adjust setup and hold times accordingly. reconnecting the two sides. At this time the internal pulldown on READY releases. INPUT OUTPUT SIDE SIDE 55pF 20pF 1V/DIV 4301 F02 20ns/DIV
Figure 2. Input-Output Connection High to Low Propagation Delay
4301fb 6
