Datasheet LTC4311 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Low Voltage I2C/SMBus Accelerator |
| Pages / Page | 12 / 10 — APPLICATIONS INFORMATION. Multiple LTC4311s in Parallel. Notes on Using … |
| File Format / Size | PDF / 142 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Multiple LTC4311s in Parallel. Notes on Using the LTC4311 in LTC1694 Applications
Model Line for this Datasheet
- LTC4311CDC#PBF LTC4311CDC#TRMPBF LTC4311CDC#TRMPBF LTC4311CDC#TRPBF LTC4311CDC#TRPBF LTC4311CSC6#PBF LTC4311CSC6#TRMPBF LTC4311CSC6#TRMPBF LTC4311CSC6#TRPBF LTC4311CSC6#TRPBF LTC4311IDC#PBF LTC4311IDC#TRMPBF LTC4311IDC#TRMPBF LTC4311IDC#TRPBF LTC4311IDC#TRPBF LTC4311ISC6#PBF LTC4311ISC6#TRMPBF LTC4311ISC6#TRMPBF LTC4311ISC6#TRPBF LTC4311ISC6#TRPBF
Text Version of Document
LTC4311
APPLICATIONS INFORMATION
t = –13kΩ• 400pF • high) at the end of the last bit sent and the slave device 2 ⎧ pulling the SDA line low before the rising edge of the ACK 2.1V + 0.15V – 3.3V – 13kΩ• 2.5mA ⎫ In ⎨ ⎬ = 0.205µs clock pulse. 0.9V – 3.3V – 13kΩ• 2.5mA ⎩ ⎭ (20) The LTC4311 5mA pull-up current is activated when the host releases the SDA line, allowing the voltage to rise above the LTC4311’s comparator threshold (VTHR). If t = t + t = 0.515µs + 0.205µs = 0.72µs r 1 2 a slave device has a high value of RS, a longer time is (21) required for the slave device to pull SDA low before the rising edge of the ACK clock pulse. To ensure suffi cient t = 293Ω• 400pF • f data setup time for ACK, slave devices with high values ⎧ 2.1V + 0.15V ⎫ of RS should pull the SDA low earlier. • (13kΩ + 300Ω) – 300Ω ⎪ ⎪ In 3.3V ⎨ ⎬ An alternative is the slave device can hold the SCL line low 0.8V – 0.15V ⎪ • (13kΩ + 300Ω) – 300Ω ⎪ until the SDA line reaches a stable state. Then, SCL can ⎩ 3.3V ⎭ be released to generate the ACK clock pulse. = 0.156µs (22)
Multiple LTC4311s in Parallel
In very heavily loaded systems, stronger pull up current The rise time meets the 1μs SMBus requirement and the may be desired. Two LTC4311’s may be used in parallel fall time meets the 0.3μs requirement. The VOL is satisfi ed to increase the total pull up current to meet rise time while meeting the minimum slew rate requirements, so RP requirements. is chosen to be 13kΩ. If the rise time was not met due to a large t1, equation 6 can be used to calculate a maximum
Notes on Using the LTC4311 in LTC1694 Applications
value of RP that will meet the rise time requirements. Although the LTC1694 and LTC4311 are functionally similar
ACK Data Setup Time
accelerators for I2C, SMBus, and other comparable open drain/collector bus applications, the LTC4311 offers a lower Care must be taken in selecting the value of RS (in series power, higher performance solution in a smaller package with the pull-down driver) to ensure that the data setup as compared to the LTC1694. These and other differences time requirement for ACK (acknowledge) is fulfi lled. An are listed in Table 1 and must be accounted for if using acknowledge is the host releasing the SDA line (pulling the LTC4311 in LTC1694 applications.
Table 1. Differences Between LTC1694 and LTC4311 SPECIFICATION LTC1694 LTC4311 COMMENTS
Enable Pin (typ) N/A 1V Allows the LTC4311 to be Disabled, Consuming Less than 5μA VCC 2.7V – 6V 1.6V – 5.5V Lower Operating Supply Voltage for Low Voltage Systems ICC (typ), BUS1, BUS2 High 60μA 26μA Lower Standby Current to Conserve Power VTHRES (typ) 0.65V Dependent on VCC Tighter, Higher Noise Margins and Improved Rise Times IPULL-UP (typ) 2.2mA 5mA Stronger Slew-Limited Source Current for Slewing Higher Bus Capacitances fMAX 100kHz 400kHz Higher Operating Frequency for I2C’s Fast Mode Bus Specifi cation 4311fa 10
APPLICATIONS INFORMATION
t = –13kΩ• 400pF • high) at the end of the last bit sent and the slave device 2 ⎧ pulling the SDA line low before the rising edge of the ACK 2.1V + 0.15V – 3.3V – 13kΩ• 2.5mA ⎫ In ⎨ ⎬ = 0.205µs clock pulse. 0.9V – 3.3V – 13kΩ• 2.5mA ⎩ ⎭ (20) The LTC4311 5mA pull-up current is activated when the host releases the SDA line, allowing the voltage to rise above the LTC4311’s comparator threshold (VTHR). If t = t + t = 0.515µs + 0.205µs = 0.72µs r 1 2 a slave device has a high value of RS, a longer time is (21) required for the slave device to pull SDA low before the rising edge of the ACK clock pulse. To ensure suffi cient t = 293Ω• 400pF • f data setup time for ACK, slave devices with high values ⎧ 2.1V + 0.15V ⎫ of RS should pull the SDA low earlier. • (13kΩ + 300Ω) – 300Ω ⎪ ⎪ In 3.3V ⎨ ⎬ An alternative is the slave device can hold the SCL line low 0.8V – 0.15V ⎪ • (13kΩ + 300Ω) – 300Ω ⎪ until the SDA line reaches a stable state. Then, SCL can ⎩ 3.3V ⎭ be released to generate the ACK clock pulse. = 0.156µs (22)
Multiple LTC4311s in Parallel
In very heavily loaded systems, stronger pull up current The rise time meets the 1μs SMBus requirement and the may be desired. Two LTC4311’s may be used in parallel fall time meets the 0.3μs requirement. The VOL is satisfi ed to increase the total pull up current to meet rise time while meeting the minimum slew rate requirements, so RP requirements. is chosen to be 13kΩ. If the rise time was not met due to a large t1, equation 6 can be used to calculate a maximum
Notes on Using the LTC4311 in LTC1694 Applications
value of RP that will meet the rise time requirements. Although the LTC1694 and LTC4311 are functionally similar
ACK Data Setup Time
accelerators for I2C, SMBus, and other comparable open drain/collector bus applications, the LTC4311 offers a lower Care must be taken in selecting the value of RS (in series power, higher performance solution in a smaller package with the pull-down driver) to ensure that the data setup as compared to the LTC1694. These and other differences time requirement for ACK (acknowledge) is fulfi lled. An are listed in Table 1 and must be accounted for if using acknowledge is the host releasing the SDA line (pulling the LTC4311 in LTC1694 applications.
Table 1. Differences Between LTC1694 and LTC4311 SPECIFICATION LTC1694 LTC4311 COMMENTS
Enable Pin (typ) N/A 1V Allows the LTC4311 to be Disabled, Consuming Less than 5μA VCC 2.7V – 6V 1.6V – 5.5V Lower Operating Supply Voltage for Low Voltage Systems ICC (typ), BUS1, BUS2 High 60μA 26μA Lower Standby Current to Conserve Power VTHRES (typ) 0.65V Dependent on VCC Tighter, Higher Noise Margins and Improved Rise Times IPULL-UP (typ) 2.2mA 5mA Stronger Slew-Limited Source Current for Slewing Higher Bus Capacitances fMAX 100kHz 400kHz Higher Operating Frequency for I2C’s Fast Mode Bus Specifi cation 4311fa 10
