Datasheet LT5538 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 40MHz to 3.8GHz RF Power Detector with 75dB Dynamic Range |
| Pages / Page | 12 / 7 — PIN FUNCTIONS. ENBL (Pin 1):. GND (Pin 4, Exposed Pad Pin 9):. VCC (Pin … |
| File Format / Size | PDF / 241 Kb |
| Document Language | English |
PIN FUNCTIONS. ENBL (Pin 1):. GND (Pin 4, Exposed Pad Pin 9):. VCC (Pin 5):. CAP–, CAP+ (Pins 6, 7):. IN+ (Pin 2):. IN– (Pin 3):
Model Line for this Datasheet
Text Version of Document
LT5538
PIN FUNCTIONS ENBL (Pin 1):
Enable Pin. An applied voltage above 1V will This pin should be connected to ground with an external activate the bias for the IC. For an applied voltage below ac-decoupling capacitor for low frequency operation. 0.3V, the circuits will be shut down (disabled) with a cor-
GND (Pin 4, Exposed Pad Pin 9):
Circuit Ground Return responding reduction in power supply current. If the enable for the entire IC. This pin must be soldered to the printed function is not required, then this pin can be connected circuit board ground plane. to VCC. Typical enable pin input currents are 100μA for EN = 3V and 200μA for EN = 5V, respectively. Note that at
VCC (Pin 5):
Power Supply Pin. This pin should be de- no time should the ENBL pin voltage be allowed to exceed coupled using 100pF and 0.1μF capacitors. VCC by more than 0.3V.
CAP–, CAP+ (Pins 6, 7):
Optional Filter Capacitor Pins.
IN+ (Pin 2):
RF Input Pin. The pin is internally biased to These pins are internally connected to the detector outputs V in front of the output buffer amplifi er. An external low-pass CC –0.5V and should be DC blocked externally. The input is connected via internal 394Ω resistor to the IN– pin which fi ltering can be formed by connecting a capacitor to Vcc should be connected to ground with an ac-decoupling from each pin for fi ltering a low frequency modulation sig- capacitor. nal. See the Applications Information section for detail.
IN– (Pin 3):
AC Ground Pin. The pin is internally biased to
OUT (Pin 8):
Detector DC Output Pin. VCC –0.5V and coupled to ground via internal 20pF capacitor.
BLOCK DIAGRAM
5 VCC DC OFFSET CANCELLATION 1 ENBL IN+ 2 RF LIMITER RF LIMITER RF LIMITER RF LIMITER RF LIMITER IN– 3 RF DETECTOR CELLS 8 OUT 4 9 6 7 5538 BD01 GND CAP– CAP+ 5538f 7
PIN FUNCTIONS ENBL (Pin 1):
Enable Pin. An applied voltage above 1V will This pin should be connected to ground with an external activate the bias for the IC. For an applied voltage below ac-decoupling capacitor for low frequency operation. 0.3V, the circuits will be shut down (disabled) with a cor-
GND (Pin 4, Exposed Pad Pin 9):
Circuit Ground Return responding reduction in power supply current. If the enable for the entire IC. This pin must be soldered to the printed function is not required, then this pin can be connected circuit board ground plane. to VCC. Typical enable pin input currents are 100μA for EN = 3V and 200μA for EN = 5V, respectively. Note that at
VCC (Pin 5):
Power Supply Pin. This pin should be de- no time should the ENBL pin voltage be allowed to exceed coupled using 100pF and 0.1μF capacitors. VCC by more than 0.3V.
CAP–, CAP+ (Pins 6, 7):
Optional Filter Capacitor Pins.
IN+ (Pin 2):
RF Input Pin. The pin is internally biased to These pins are internally connected to the detector outputs V in front of the output buffer amplifi er. An external low-pass CC –0.5V and should be DC blocked externally. The input is connected via internal 394Ω resistor to the IN– pin which fi ltering can be formed by connecting a capacitor to Vcc should be connected to ground with an ac-decoupling from each pin for fi ltering a low frequency modulation sig- capacitor. nal. See the Applications Information section for detail.
IN– (Pin 3):
AC Ground Pin. The pin is internally biased to
OUT (Pin 8):
Detector DC Output Pin. VCC –0.5V and coupled to ground via internal 20pF capacitor.
BLOCK DIAGRAM
5 VCC DC OFFSET CANCELLATION 1 ENBL IN+ 2 RF LIMITER RF LIMITER RF LIMITER RF LIMITER RF LIMITER IN– 3 RF DETECTOR CELLS 8 OUT 4 9 6 7 5538 BD01 GND CAP– CAP+ 5538f 7
