Datasheet ISL97634 (Intersil) - 10

link to page 10 link to page 10 link to page 10 link to page 10 ISL97634 may be beneficial enough that it outweighs the disadvantage of diode if the output voltage is low. The L2 series resistance also adding additional component cost. L1 and L2 can be a coupled contributes additional loss. Figure 20 shows the efficiency inductor in one package. measurement of a single LED application as the input varies between 2.7V and 4.2V.
L1 V C3 D0 IN = 2.7V TO 5.5V 1 2 VA VB
Note VB is considered the level-shifted LX node of a standard boost
C1 22µH 1µF
regulator. The higher the input voltage, the lower the V
C4 0.22µF
B voltage
1µF L2
will be during PWM on period. The result is that the efficiency will
22µH D1
be lower at higher input voltages because the SEPIC has to work
VIN LX
harder to boost up to the required level. This behavior is the
C2 VOUT
opposite to the standard boost regulator’s and the comparison is
0.1µF ISL97634 FBSW
shown in Figure 20.
FB SDIN GND 76 R1 1 VIN = 2.7V ) 72 VIN = 4.2V
FIGURE 19. SEPIC LED DRIVER The simplest way to understand SEPIC topology is to think about it
68
as a boost regulator where the input voltage is level shifted
1 LED
downward at the same magnitude and the lowest reference level
L EFFICIENCY (% 64 1 = L2 = 22µH
starts at -VIN rather than 0V.
C3 = 1µF
The SEPIC works as follows; assume the circuit in Figure 19
R1 = 4.7
operates normally when the ISL97634 internal switch opens and it
60 0 5 10 15 20
is in the PWM off state. After a short duration where few LC time
ILED (mA)
constants elapsed, the circuit is considered in the steady-state FIGURE 20. EFFICIENCY MEASUREMENT OF A SINGLE LED SEPIC within the PWM off period that L DRIVER 1 and L2 are shorted. VB is therefore shorted to the ground and C3 is charged to VIN with PCB Layout Considerations VA = VIN. When the ISL97634 internal switch closes and the circuit is in the PWM on-state, V The layout is very important for the converter to function properly. A is now pulled to ground. Since the voltage in C R 3 cannot be changed instantaneously, VB is shifted SET must be located as close as possible to the FB and GND pins. downward and becomes -V Longer traces to the LEDs are acceptable. Similarly, the supply IN. The next cycle when the ISL97634 switch opens, V decoupling cap and the output filter cap should be as close as B boosts up to the targeted output like the standard boost regulator operation, except the lowest reference possible to the VIN and VOUT pins. point is at -VIN. The output is approximated in Equation 9: The heat of the IC is mainly dissipated through the thermal pad of D = --------- the package. Maximizing the copper area connected to this pad if VOUT VIN1 – D (EQ. 9) possible and connect to ground plane on the PCB. Connect all vias to where D is the on-time of the PWM duty cycle. the correct voltage potential (power plane) indicated in the The convenience of SEPIC comes with some trade-off in addition datasheet. In addition, a solid ground plane is always helpful for the to the additional L and C costs. The efficiency is usually lowered EMI performance. because of the relatively large efficiency loss through the Schottky © Copyright Intersil Americas LLC 2006-2013. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6264 Rev 4.00 Page 10 of 12 August 27, 2013