Datasheet AD7741, AD7742 (Analog Devices) - 9

AD7741/AD7742
The digital data that represents the analog input voltage is con- tained in the duty cycle of the pulse train appearing at the out-
AD7741/AD7742
put of the comparator. The output is a fixed-width pulse whose frequency depends on the analog input signal. The input voltage
TO OTHER CIRCUITRY
is offset internally so that a full-scale input gives an output fre- quency of 0.45 fCLKIN and zero-scale input gives an output fre-
5M
V quency of 0.05 fCLKIN. The output allows simple interfacing to either standard logic families or opto-couplers. The clock high
CLKIN CLKOUT
period controls the pulsewidth of the frequency output. The pulse is initiated by the edge of the clock signal. The delay time
C1 C2
between the edge of the clock and the edge of the frequency output is typically 9 ns. Figure 7 shows the waveform of this Figure 8. On-Chip Oscillator frequency output. The on-chip oscillator circuit also has a start-up time associated After power-up, or if there is a step change in input voltage, with it before it oscillates at its correct frequency and correct there is a settling time that must elapse before valid data is voltage levels. The typical start-up time for the circuit is 5 ms obtained. This is typically 2 CLKIN cycles on the AD7742 and (with a 6.144 MHz crystal). 10 CLKIN cycles on the AD7741. The AD7741/AD7742 master clock appears on the CLKOUT pin of the device. The maximum recommended load on this pin
fCLKIN
is one CMOS load. When using a crystal to generate the AD7741/ AD7742 clock it may be desirable to then use this clock as the clock source for the system. In this case it is recommended that
fOUT = fCLKIN/4 VIN = VREF/2
the CLKOUT signal be buffered with a CMOS buffer before being applied to the rest of the circuit.
fOUT = fCLKIN/10 V Reference Input IN = VREF/8
The AD7741/AD7742 performs conversion relative to an applied
f
reference voltage that allows easy interfacing to ratiometric
OUT = fCLKIN*3/20 VIN = VREF/4
systems. This reference may be applied using the internal 2.5 V bandgap reference. For the AD7741, this is done by simply
6 TCLK 7 TCLK
leaving REFIN/OUT unconnected. For the AD7742, REFIN is
AVERAGE fOUT IS fCLKIN *3/20 BUT THE ACTUAL PULSE STREAM
tied to REFOUT. Alternatively, an external reference, e.g.,
VARIES BETWEEN fCLKIN/6 AND fCLKIN/7
REF192 or AD780, may be used. For the AD7741, this is con- Figure 7. AD7741/AD7742 Frequency Output Waveforms nected to REFIN/OUT and will overdrive the internal refer- ence. For the AD7742, it is connected directly to the REFIN
Clock Generation
pin. As distinct from the asynchronous VFCs which rely on the stability of an external capacitor to set their full-scale frequency, the While the internal reference will be adequate for most applica- AD7741/AD7742 uses an external clock to define the full-scale tions, power supply rejection and overall regulation may be output frequency. The result is a more stable, more linear trans- improved through the use of an external precision reference. fer function and also allows the designer to determine the sys- The process of selecting an external voltage reference should tem stability and drift based upon the external clock selected. A include consideration of drive capability, initial error, noise and crystal oscillator may also be used if desired. drift characteristics. A suitable choice would be the AD780 or REF192. The AD7741/AD7742 requires a master clock input, which may be an external CMOS-compatible clock signal applied to the
Power-Down Mode
CLKIN pin (CLKOUT not used). Alternatively, a crystal of the The low power standby mode is initiated by taking the PD pin correct frequency can be connected between CLKIN and low, which shuts down most of the analog and digital circuitry. CLKOUT, when the clock circuit will function as a crystal This reduces the power consumption to 185 µW max. controlled oscillator. Figure 8 shows a simple model of the on- chip oscillator. REV. 0 –9–