Datasheet ADIS16445 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Compact, Precision Six Degrees of Freedom Inertial Sensor |
| Pages / Page | 23 / 6 — Data Sheet. ADIS16445. TIMING SPECIFICATIONS. Table 2. Normal Mode. Burst … |
| Revision | I |
| File Format / Size | PDF / 499 Kb |
| Document Language | English |
Data Sheet. ADIS16445. TIMING SPECIFICATIONS. Table 2. Normal Mode. Burst Read. Parameter. Description. Min1. Typ. Max. Unit. Timing Diagrams
Model Line for this Datasheet
Text Version of Document
link to page 6
Data Sheet ADIS16445 TIMING SPECIFICATIONS
TA = 25°C, VDD = +3.3 V, unless otherwise noted.
Table 2. Normal Mode Burst Read Parameter Description Min1 Typ Max Min1 Typ Max Unit
fSCLK Serial clock 0.01 2.0 0.01 1.0 MHz tSTALL Stall period between data 9 N/A2 µs tREADRATE Read rate 40 µs t Chip select to SCLK edge 48.8 48.8 ns CS tDAV DOUT valid after SCLK edge 100 100 ns tDSU DIN setup time before SCLK rising edge 24.4 24.4 ns tDHD DIN hold time after SCLK rising edge 48.8 48.8 ns tSCLKR, tSCLKF SCLK rise/fall times, not shown in timing diagrams 5 12.5 5 12.5 ns tDR, tDF DOUT rise/fal times, not shown in timing diagrams 5 12.5 5 12.5 ns tSFS CS high after SCLK edge 5 5 ns t1 Input sync positive pulse width 25 25 µs tSTDR Input sync to data ready valid transition 670 670 µs tNV Data invalid time 210 210 µs t3 Input sync period 910 910 µs 1 Guaranteed by design and characterization, but not tested in production. 2 When using the burst read mode, the stall period is not applicable.
Timing Diagrams CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN R/W A6 A5 A4 A3 A2 D2 D1 LSB
002 1051- 1 Figure 2. SPI Timing and Sequence
tREADRATE tSTALL CS SCLK
003 1051- 1 Figure 3. Stall Time and Data Rate
t3 t t STDR 1 CLOCK DATA READY
004
tNV
1051- 1 Figure 4. Input Clock Timing Diagram Rev. F | Page 5 of 22 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics User Registers User Interface Reading Sensor Data Burst Read Function SPI Read Test Sequence Device Configuration Dual Memory Structure Output Data Registers Gyroscopes Accelerometers Internal Temperature System Functions Global Commands Product Identification Self-Test Function Status/Error Flags Memory Management Checksum Test Input/Output Configuration Data Ready Indicator General-Purpose Input/Output Example Input/Output Configuration Digital Processing Configuration Gyroscopes/Accelerometers Input Clock Configuration Digital Filtering Dynamic Range Calibration Gyroscopes Gyroscope Bias Error Estimation Gyroscope Bias Correction Factors Single Command Bias Correction Accelerometers Accelerometer Bias Error Estimation Accelerometer Bias Correction Factors Point of Percussion Alignment Flash Updates Restoring Factory Calibration Alarms Static Alarm Use Dynamic Alarm Use Alarm Reporting Alarm Example Applications Information Mounting Tips Power Supply Considerations ADIS16445/PCBZ Installation PC-Based Evaluation Tools Outline Dimensions Ordering Guide
Data Sheet ADIS16445 TIMING SPECIFICATIONS
TA = 25°C, VDD = +3.3 V, unless otherwise noted.
Table 2. Normal Mode Burst Read Parameter Description Min1 Typ Max Min1 Typ Max Unit
fSCLK Serial clock 0.01 2.0 0.01 1.0 MHz tSTALL Stall period between data 9 N/A2 µs tREADRATE Read rate 40 µs t Chip select to SCLK edge 48.8 48.8 ns CS tDAV DOUT valid after SCLK edge 100 100 ns tDSU DIN setup time before SCLK rising edge 24.4 24.4 ns tDHD DIN hold time after SCLK rising edge 48.8 48.8 ns tSCLKR, tSCLKF SCLK rise/fall times, not shown in timing diagrams 5 12.5 5 12.5 ns tDR, tDF DOUT rise/fal times, not shown in timing diagrams 5 12.5 5 12.5 ns tSFS CS high after SCLK edge 5 5 ns t1 Input sync positive pulse width 25 25 µs tSTDR Input sync to data ready valid transition 670 670 µs tNV Data invalid time 210 210 µs t3 Input sync period 910 910 µs 1 Guaranteed by design and characterization, but not tested in production. 2 When using the burst read mode, the stall period is not applicable.
Timing Diagrams CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN R/W A6 A5 A4 A3 A2 D2 D1 LSB
002 1051- 1 Figure 2. SPI Timing and Sequence
tREADRATE tSTALL CS SCLK
003 1051- 1 Figure 3. Stall Time and Data Rate
t3 t t STDR 1 CLOCK DATA READY
004
tNV
1051- 1 Figure 4. Input Clock Timing Diagram Rev. F | Page 5 of 22 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics User Registers User Interface Reading Sensor Data Burst Read Function SPI Read Test Sequence Device Configuration Dual Memory Structure Output Data Registers Gyroscopes Accelerometers Internal Temperature System Functions Global Commands Product Identification Self-Test Function Status/Error Flags Memory Management Checksum Test Input/Output Configuration Data Ready Indicator General-Purpose Input/Output Example Input/Output Configuration Digital Processing Configuration Gyroscopes/Accelerometers Input Clock Configuration Digital Filtering Dynamic Range Calibration Gyroscopes Gyroscope Bias Error Estimation Gyroscope Bias Correction Factors Single Command Bias Correction Accelerometers Accelerometer Bias Error Estimation Accelerometer Bias Correction Factors Point of Percussion Alignment Flash Updates Restoring Factory Calibration Alarms Static Alarm Use Dynamic Alarm Use Alarm Reporting Alarm Example Applications Information Mounting Tips Power Supply Considerations ADIS16445/PCBZ Installation PC-Based Evaluation Tools Outline Dimensions Ordering Guide
