Datasheet LT1336 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Half-Bridge N-Channel Power MOSFET Driver with Boost Regulator |
| Pages / Page | 20 / 7 — pin FuncTions. ISENSE (Pin 1):. BGATEDR (Pin 9):. SV+ (Pin 2):. PV+ (Pin … |
| File Format / Size | PDF / 268 Kb |
| Document Language | English |
pin FuncTions. ISENSE (Pin 1):. BGATEDR (Pin 9):. SV+ (Pin 2):. PV+ (Pin 10):. INTOP (Pin 3):. TSOURCE (Pin 11):. TGATEFB (Pin 12):
Model Line for this Datasheet
Text Version of Document
LT1336
pin FuncTions ISENSE (Pin 1):
Boost Regulator ISENSE Comparator Input.
BGATEDR (Pin 9):
Bottom Gate Drive. The high current An RSENSE placed between Pin 1 and V+ sets the maximum drive point for the bottom MOSFET. When a gate resistor peak current. Pin 1 can be left open if the boost regulator is used it is inserted between Pin 9 and the gate of the is not used. MOSFET.
SV+ (Pin 2):
Main Signal Supply. Must be closely decoupled
PV+ (Pin 10):
Bottom Driver Supply. Must be connected to the signal ground Pin 6. to the same supply as Pin 2.
INTOP (Pin 3):
Top Driver Input. Pin 3 is disabled when
TSOURCE (Pin 11):
Top Driver Return. Connects to the top Pin 4 is high. A 3k input resistor followed by a 5V internal MOSFET source and the low side of the bootstrap capacitor. clamp prevents saturation of the input transistors.
TGATEFB (Pin 12):
Top Gate Feedback. Must connect
INBOTTOM (Pin 4):
Bottom Driver Input. Pin 4 is disabled directly to the top power MOSFET gate. The bottom when Pin 3 is high. A 3k input resistor followed by a 5V MOSFET turn-on is inhibited until VTGATE FB – VTSOURCE internal clamp prevents saturation of the input transistors. has discharged to below 2.9V.
UVOUT (Pin 5):
Undervoltage Output. Open collector
TGATEDR (Pin 13):
Top Gate Drive. The high current drive NPN output which turns on when V+ drops below the point for the top MOSFET. When a gate resistor is used it undervoltage threshold. is inserted between Pin 13 and the gate of the MOSFET.
SGND (Pin 6):
Small-Signal Ground. Must be routed
BOOST (Pin 14):
Top Driver Supply. Connects to the high separately from other grounds to the system ground. side of the bootstrap capacitor.
PGND (Pin 7):
Bottom Driver Power Ground. Connects to
SWGND (Pin 15):
Boost Regulator Ground. Must be routed source of bottom N-channel MOSFET. separately from the other grounds to the system ground.
BGATEFB (Pin 8):
Bottom Gate Feedback. Must connect Pin 15 can be left open if the boost regulator is not used. directly to the bottom power MOSFET gate. The top
SWITCH (Pin 16):
Boost Regulator Switch. Connect this MOSFET turn-on is inhibited until Pin 8 has discharged pin to the inductor/diode of the boost regulator network. to below 2.5V. Pin 16 can be left open if the boost regulator is not used. 1336fa 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Test Circuit Timing Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
pin FuncTions ISENSE (Pin 1):
Boost Regulator ISENSE Comparator Input.
BGATEDR (Pin 9):
Bottom Gate Drive. The high current An RSENSE placed between Pin 1 and V+ sets the maximum drive point for the bottom MOSFET. When a gate resistor peak current. Pin 1 can be left open if the boost regulator is used it is inserted between Pin 9 and the gate of the is not used. MOSFET.
SV+ (Pin 2):
Main Signal Supply. Must be closely decoupled
PV+ (Pin 10):
Bottom Driver Supply. Must be connected to the signal ground Pin 6. to the same supply as Pin 2.
INTOP (Pin 3):
Top Driver Input. Pin 3 is disabled when
TSOURCE (Pin 11):
Top Driver Return. Connects to the top Pin 4 is high. A 3k input resistor followed by a 5V internal MOSFET source and the low side of the bootstrap capacitor. clamp prevents saturation of the input transistors.
TGATEFB (Pin 12):
Top Gate Feedback. Must connect
INBOTTOM (Pin 4):
Bottom Driver Input. Pin 4 is disabled directly to the top power MOSFET gate. The bottom when Pin 3 is high. A 3k input resistor followed by a 5V MOSFET turn-on is inhibited until VTGATE FB – VTSOURCE internal clamp prevents saturation of the input transistors. has discharged to below 2.9V.
UVOUT (Pin 5):
Undervoltage Output. Open collector
TGATEDR (Pin 13):
Top Gate Drive. The high current drive NPN output which turns on when V+ drops below the point for the top MOSFET. When a gate resistor is used it undervoltage threshold. is inserted between Pin 13 and the gate of the MOSFET.
SGND (Pin 6):
Small-Signal Ground. Must be routed
BOOST (Pin 14):
Top Driver Supply. Connects to the high separately from other grounds to the system ground. side of the bootstrap capacitor.
PGND (Pin 7):
Bottom Driver Power Ground. Connects to
SWGND (Pin 15):
Boost Regulator Ground. Must be routed source of bottom N-channel MOSFET. separately from the other grounds to the system ground.
BGATEFB (Pin 8):
Bottom Gate Feedback. Must connect Pin 15 can be left open if the boost regulator is not used. directly to the bottom power MOSFET gate. The top
SWITCH (Pin 16):
Boost Regulator Switch. Connect this MOSFET turn-on is inhibited until Pin 8 has discharged pin to the inductor/diode of the boost regulator network. to below 2.5V. Pin 16 can be left open if the boost regulator is not used. 1336fa 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Test Circuit Timing Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
