Datasheet PIC18(L)F24/25K40 (Microchip)

PIC18(L)F24/25K40 28-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology Description
These PIC18(L)F24/25K40 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals, combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications. These 28 -pin devices are equipped with a 10-bit ADC with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and performing automatic threshold comparisons. They also offer a set of Core Independent Peripherals such as Complementary Waveform Generator (CWG), Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/Memory Scan, Zero-Cross Detect (ZCD) and Peripheral Pin Select (PPS), providing for increased design flexibility and lower system cost.
Core Features
• C Compiler Optimized RISC Architecture • Operating Speed: – DC – 64 MHz clock input over the full VDD range – 62.5 ns minimum instruction cycle • Programmable 2-Level Interrupt Priority • 31-Level Deep Hardware Stack • Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT) • Four 16-Bit Timers (TMR0/1/3/5) • Low-Current Power-on Reset (POR) • Power-up Timer (PWRT) • Brown-out Reset (BOR) • Low-Power BOR (LPBOR) Option • Windowed Watchdog Timer (WWDT): – Watchdog Reset on too long or too short interval between watchdog clear events – Variable prescaler selection – Variable window size selection – All sources configurable in hardware or software
Memory
• Up to 32K bytes Program Flash Memory • Up to 2048 Bytes Data SRAM Memory © 2017 Microchip Technology Inc.
Datasheet
40001843D-page 1 Document Outline Description Core Features Memory Operating Characteristics Power-Saving Operation Modes eXtreme Low-Power (XLP) Features Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features PIC18(L)F24/25K40 Family Types Pin Diagrams Pin Allocation Tables Table of Contents 1. Device Overview 1.1. New Core Features 1.1.1. XLP Technology 1.1.2. Multiple Oscillator Options and Features 1.2. Other Special Features 1.3. Details on Individual Family Members 1.4. Register and Bit naming conventions 1.4.1. Register Names 1.4.2. Bit Names 1.4.2.1. Short Bit Names 1.4.2.2. Long Bit Names 1.4.2.3. Bit Fields 1.4.3. Register and Bit Naming Exceptions 1.4.3.1. Status, Interrupt, and Mirror Bits 1.4.3.2. Legacy Peripherals 2. Guidelines for Getting Started with PIC18(L)F24/25K40 Microcontrollers 2.1. Basic Connection Requirements 2.2. Power Supply Pins 2.2.1. Decoupling Capacitors 2.2.2. Tank Capacitors 2.3. Master Clear (MCLR) Pin 2.4. In-Circuit Serial Programming™ ICSP™ Pins 2.5. External Oscillator Pins 2.6. Unused I/Os 3. Device Configuration 3.1. Configuration Words 3.2. Code Protection 3.2.1. Program Memory Protection 3.2.2. Data Memory Protection 3.3. Write Protection 3.4. User ID 3.5. Device ID and Revision ID 3.6. Register Summary - Configuration Words 3.7. Register Definitions: Configuration Words 3.7.1. CONFIG1 3.7.2. CONFIG2 3.7.3. CONFIG3 3.7.4. CONFIG4 3.7.5. CONFIG5 3.7.6. CONFIG6 3.8. Register Summary - Device and Revision 3.9. Register Definitions: Device and Revision 3.9.1. DEVICE ID 3.9.2. REVISION ID 4. Oscillator Module (with Fail-Safe Clock Monitor) 4.1. Overview 4.2. Clock Source Types 4.2.1. External Clock Sources 4.2.1.1. EC Mode 4.2.1.2. LP, XT, HS Modes 4.2.1.3. Oscillator Start-up Timer (OST) 4.2.1.4. 4x PLL 4.2.1.5. Secondary Oscillator 4.2.2. Internal Clock Sources 4.2.2.1. HFINTOSC 4.2.2.2. MFINTOSC 4.2.2.3. LFINTOSC 4.2.2.4. ADCRC (also referred to as FRC) 4.2.3. Oscillator Status and Adjustments 4.2.3.1. Internal Oscillator Frequency Adjustment 4.2.3.2. Oscillator Status and Manual Enable 4.2.3.3. HFOR and MFOR Bits 4.3. Clock Switching 4.3.1. New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) Bits 4.3.2. PLL Input Switch 4.3.3. Clock Switch and Sleep 4.4. Fail-Safe Clock Monitor 4.4.1. Fail-Safe Detection 4.4.2. Fail-Safe Operation 4.4.3. Fail-Safe Condition Clearing 4.4.4. Reset or Wake-up from Sleep 4.5. Register Summary - OSC 4.6. Register Definitions: Oscillator Control 4.6.1. OSCCON1 4.6.2. OSCCON2 4.6.3. OSCCON3 4.6.4. OSCSTAT 4.6.5. OSCFRQ 4.6.6. OSCTUNE 4.6.7. OSCEN 5. Reference Clock Output Module 5.1. Clock Source 5.1.1. Clock Synchronization 5.2. Programmable Clock Divider 5.3. Selectable Duty Cycle 5.4. Operation in Sleep Mode 5.5. Register Summary: Reference CLK 5.6. Register Definitions: Reference Clock 5.6.1. CLKRCON 5.6.2. CLKRCLK 6. Power-Saving Operation Modes 6.1. Doze Mode 6.1.1. Doze Operation 6.1.2. Interrupts During Doze 6.2. Sleep Mode 6.2.1. Wake-up from Sleep 6.2.2. Wake-up Using Interrupts 6.2.3. Low-Power Sleep Mode 6.2.3.1. Sleep Current vs. Wake-up Time 6.2.3.2. Peripheral Usage in Sleep 6.2.4. Idle Mode 6.2.4.1. Idle and Interrupts 6.2.4.2. Idle and WWDT 6.3. Peripheral Operation in Power-Saving Modes 6.4. Register Summary - Power Savings Control 6.5. Register Definitions: Power Savings Control 6.5.1. VREGCON 6.5.2. CPUDOZE 7. (PMD) Peripheral Module Disable 7.1. Disabling a Module 7.2. Enabling a Module 7.3. Register Summary - PMD 7.4. Register Definitions: Peripheral Module Disable 7.4.1. PMD0 7.4.2. PMD1 7.4.3. PMD2 7.4.4. PMD3 7.4.5. PMD4 7.4.6. PMD5 8. Resets 8.1. Power-on Reset (POR) 8.2. Brown-out Reset (BOR) 8.2.1. BOR is Always On 8.2.2. BOR is OFF in Sleep 8.2.3. BOR Controlled by Software 8.2.4. BOR and Bulk Erase 8.3. Low-Power Brown-out Reset (LPBOR) 8.3.1. Enabling LPBOR 8.3.1.1. LPBOR Module Output 8.4. MCLR 8.4.1. MCLR Enabled 8.4.2. MCLR Disabled 8.5. Windowed Watchdog Timer (WWDT) Reset 8.6. RESET Instruction 8.7. Stack Overflow/Underflow Reset 8.8. Programming Mode Exit 8.9. Power-up Timer (PWRT) 8.10. Start-up Sequence 8.11. Determining the Cause of a Reset 8.12. Power Control (PCON0) Register 8.13. Register Summary - BOR Control and Power Control 8.14. Register Definitions: Power Control 8.14.1. BORCON 8.14.2. PCON0 9. (WWDT) Windowed Watchdog Timer 9.1. Independent Clock Source 9.2. WWDT Operating Modes 9.2.1. WWDT Is Always On 9.2.2. WWDT Is Off in Sleep 9.2.3. WWDT Controlled by Software 9.3. Time-out Period 9.4. Watchdog Window 9.5. Clearing the WWDT 9.5.1. CLRWDT Considerations (Windowed Mode) 9.6. Operation During Sleep 9.7. Register Summary - WDT Control 9.8. Register Definitions: Windowed Watchdog Timer Control 9.8.1. WDTCON0 9.8.2. WDTCON1 9.8.3. WDTPS 9.8.4. WDTTMR 10. Memory Organization 10.1. Program Memory Organization 10.1.1. Program Counter 10.1.2. Return Address Stack 10.1.2.1. Top-of-Stack Access 10.1.2.2. Return Stack Pointer 10.1.2.3. Stack Overflow and Underflow Resets 10.1.2.4. PUSH and POP Instructions 10.1.2.5. Fast Register Stack 10.1.3. Look-up Tables in Program Memory 10.1.3.1. Computed GOTO 10.1.3.2. Table Reads and Table Writes 10.2. PIC18 Instruction Cycle 10.2.1. Clocking Scheme 10.2.2. Instruction Flow/Pipelining 10.2.3. Instructions in Program Memory 10.2.4. Two-Word Instructions 10.3. Data Memory Organization 10.3.1. Bank Select Register 10.3.2. Access Bank 10.3.3. General Purpose Register File 10.3.4. Special Function Registers 10.3.5. Status Register 10.4. Data Addressing Modes 10.4.1. Inherent and Literal Addressing 10.4.2. Direct Addressing 10.4.3. Indirect Addressing 10.4.3.1. FSR Registers and the INDF Operand 10.4.3.2. FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW 10.4.3.3. Operations by FSRs on FSRs 10.5. Data Memory and the Extended Instruction Set 10.5.1. Indexed Addressing with Literal Offset 10.5.2. Instructions Affected by Indexed Literal Offset Mode 10.5.3. Mapping the Access Bank in Indexed Literal Offset Mode 10.6. PIC18 Instruction Execution and the Extended Instruction Set 10.7. Register Summary: Memory and Status 10.8. Register Definitions: Memory and Status 10.8.1. PCL 10.8.2. PCLAT 10.8.3. TOS 10.8.4. STKPTR 10.8.5. STATUS 10.8.6. WREG 10.8.7. INDF 10.8.8. POSTDEC 10.8.9. POSTINC 10.8.10. PREINC 10.8.11. PLUSW 10.8.12. FSR 10.8.13. BSR 11. (NVM) Nonvolatile Memory Control 11.1. Program Flash Memory 11.1.1. Table Pointer Operations 11.1.1.1. Table Pointer Register 11.1.1.2. Table Latch Register 11.1.1.3. Table Read Operations 11.1.1.4. Table Write Operations 11.1.1.5. Table Pointer Boundaries 11.1.1.6. Reading the Program Flash Memory 11.1.2. NVM Unlock Sequence 11.1.3. Erasing Program Flash Memory 11.1.3.1. Program Flash Memory Erase Sequence 11.1.4. Writing to Program Flash Memory 11.1.4.1. Program Flash Memory Write Sequence 11.1.4.2. Write Verify 11.1.4.3. Unexpected Termination of Write Operation 11.1.4.4. Protection Against Spurious Writes 11.2. User ID, Device ID and Configuration Word Access 11.2.1. Reading Access 11.2.2. Writing Access 11.3. Data EEPROM Memory 11.3.1. NVMADR Register 11.3.2. NVMCON1 and NVMCON2 Registers 11.3.3. Reading the Data EEPROM Memory 11.3.4. Writing to the Data EEPROM Memory 11.3.5. Write Verify 11.3.6. Operation During Code-Protect 11.3.7. Protection Against Spurious Write 11.3.8. Erasing the Data EEPROM Memory 11.4. Register Summary: NVM Control 11.5. Register Definitions: Nonvolatile Memory 11.5.1. NVMCON1 11.5.2. NVMCON2 11.5.3. NVMADR 11.5.4. NVMDAT 11.5.5. TBLPTR 11.5.6. TABLAT 12. 8x8 Hardware Multiplier 12.1. Introduction 12.2. Operation 12.3. Register Summary - 8x8 Hardware Multiplier 12.4. Register Definitions: 8x8 Hardware Multiplier 12.4.1. PROD 13. Cyclic Redundancy Check (CRC) Module with Memory Scanner 13.1. CRC Module Overview 13.2. CRC Functional Overview 13.3. CRC Polynomial Implementation 13.4. CRC Data Sources 13.4.1. CRC from User Data 13.4.2. CRC from Flash 13.5. CRC Check Value 13.6. CRC Interrupt 13.7. Configuring the CRC 13.8. Program Memory Scan Configuration 13.9. Scanner Interrupt 13.10. Scanning Modes 13.10.1. Burst Mode 13.10.2. Concurrent Mode 13.10.3. Triggered mode 13.10.4. Peek Mode 13.10.5. Interrupt Interaction 13.10.6. WWDT interaction 13.10.7. In-Circuit Debug (ICD) Interaction 13.10.8. Peripheral Module Disable 13.11. Register Summary - CRC 13.12. Register Definitions: CRC and Scanner Control 13.12.1. CRCCON0 13.12.2. CRCCON1 13.12.3. CRCDAT 13.12.4. CRCACC 13.12.5. CRCSHIFT 13.12.6. CRCXOR 13.12.7. SCANCON0 13.12.8. SCANLADR 13.12.9. SCANHADR 13.12.10. SCANTRIG 14. Interrupts 14.1. Mid-Range Compatibility 14.2. Interrupt Priority 14.3. Interrupt Response 14.4. INTCON Registers 14.5. PIR Registers 14.6. PIE Registers 14.7. IPR Registers 14.8. INTn Pin Interrupts 14.9. TMR0 Interrupt 14.10. Interrupt-on-Change 14.11. Context Saving During Interrupts 14.12. Register Summary - Interrupt Control 14.13. Register Definitions: Interrupt Control 14.13.1. INTCON 14.13.2. PIR0 14.13.3. PIR1 14.13.4. PIR2 14.13.5. PIR3 14.13.6. PIR4 14.13.7. PIR5 14.13.8. PIR6 14.13.9. PIR7 14.13.10. PIE0 14.13.11. PIE1 14.13.12. PIE2 14.13.13. PIE3 14.13.14. PIE4 14.13.15. PIE5 14.13.16. PIE6 14.13.17. PIE7 14.13.18. IPR0 14.13.19. IPR1 14.13.20. IPR2 14.13.21. IPR3 14.13.22. IPR4 14.13.23. IPR5 14.13.24. IPR6 14.13.25. IPR7 15. I/O Ports 15.1. I/O Priorities 15.2. PORTx Registers 15.2.1. Data Register 15.2.2. Direction Control 15.2.3. Analog Control 15.2.4. Open-Drain Control 15.2.5. Slew Rate Control 15.2.6. Input Threshold Control 15.2.7. Weak Pull-up Control 15.2.8. Edge Selectable Interrupt-on-Change 15.3. PORTE Registers 15.3.1. PORTE on 28-Pin Devices 15.3.2. RE3 Weak Pull-Up 15.3.3. PORTE Interrupt-on-Change 15.4. Register Summary - Input/Output 15.5. Register Definitions: Port Control 15.5.1. PORTA 15.5.2. PORTB 15.5.3. PORTC 15.5.4. PORTE 15.5.5. TRISA 15.5.6. TRISB 15.5.7. TRISC 15.5.8. LATA 15.5.9. LATB 15.5.10. LATC 15.5.11. ANSELA 15.5.12. ANSELB 15.5.13. ANSELC 15.5.14. WPUA 15.5.15. WPUB 15.5.16. WPUC 15.5.17. WPUE 15.5.18. ODCONA 15.5.19. ODCONB 15.5.20. ODCONC 15.5.21. SLRCONA 15.5.22. SLRCONB 15.5.23. SLRCONC 15.5.24. INLVLA 15.5.25. INLVLB 15.5.26. INLVLC 15.5.27. INLVLE 16. Interrupt-on-Change 16.1. Features 16.2. Overview 16.3. Block Diagram 16.4. Enabling the Module 16.5. Individual Pin Configuration 16.6. Interrupt Flags 16.7. Clearing Interrupt Flags 16.8. Operation in Sleep 16.9. Register Summary - Interrupt-on-Change 16.10. Register Definitions: Interrupt-on-Change Control 16.10.1. IOCAF 16.10.2. IOCBF 16.10.3. IOCCF 16.10.4. IOCEF 16.10.5. IOCAN 16.10.6. IOCBN 16.10.7. IOCCN 16.10.8. IOCEN 16.10.9. IOCAP 16.10.10. IOCBP 16.10.11. IOCCP 16.10.12. IOCEP 17. (PPS) Peripheral Pin Select Module 17.1. PPS Inputs 17.2. PPS Outputs 17.3. Bidirectional Pins 17.4. PPS Lock 17.5. PPS One-Way Lock 17.6. Operation During Sleep 17.7. Effects of a Reset 17.8. Register Summary - PPS 17.9. Register Definitions: PPS Input and Output Selection 17.9.1. Peripheral xxx Input Selection 17.9.2. Pin Rxy Output Source Selection Register 17.9.3. PPS Lock Register 18. Timer0 Module 18.1. Timer0 Operation 18.1.1. 8-bit Mode 18.1.2. 16-Bit Mode 18.2. Clock Selection 18.2.1. Clock Source Selection 18.2.2. Synchronous Mode 18.2.3. Asynchronous Mode 18.2.4. Programmable Prescaler 18.3. Timer0 Output and Interrupt 18.3.1. Programmable Postscaler 18.3.2. Timer0 Output 18.3.3. Timer0 Interrupt 18.3.4. Timer0 Example 18.4. Operation During Sleep 18.5. Register Summary - Timer0 18.6. Register Definitions: Timer0 Control 18.6.1. T0CON0 18.6.2. T0CON1 18.6.3. TMR0 19. Timer1 Module with Gate Control 19.1. Timer1 Operation 19.2. Clock Source Selection 19.2.1. Internal Clock Source 19.2.2. External Clock Source 19.3. Timer1 Prescaler 19.4. Secondary Oscillator 19.5. Timer1 Operation in Asynchronous Counter Mode 19.5.1. Reading and Writing Timer1 in Asynchronous Counter Mode 19.6. Timer1 16-Bit Read/Write Mode 19.7. Timer1 Gate 19.7.1. Timer1 Gate Enable 19.7.2. Timer1 Gate Source Selection 19.7.3. Timer1 Gate Toggle Mode 19.7.4. Timer1 Gate Single-Pulse Mode 19.7.5. Timer1 Gate Value Status 19.7.6. Timer1 Gate Event Interrupt 19.8. Timer1 Interrupt 19.9. Timer1 Operation During Sleep 19.10. CCP Capture/Compare Time Base 19.11. CCP Special Event Trigger 19.12. Peripheral Module Disable 19.13. Register Summary - Timer1 19.14. Register Definitions: Timer1 19.14.1. TxCON 19.14.2. TxGCON 19.14.3. TMRxCLK 19.14.4. TMRxGATE 19.14.5. TMRx 20. Timer2 Module 20.1. Timer2 Operation 20.1.1. Free Running Period Mode 20.1.2. One-Shot Mode 20.1.3. Monostable Mode 20.2. Timer2 Output 20.3. External Reset Sources 20.4. Timer2 Interrupt 20.5. Operating Modes 20.6. Operation Examples 20.6.1. Software Gate Mode 20.6.2. Hardware Gate Mode 20.6.3. Edge-Triggered Hardware Limit Mode 20.6.4. Level-Triggered Hardware Limit Mode 20.6.5. Software Start One-Shot Mode 20.6.6. Edge-Triggered One-Shot Mode 20.6.7. Edge-Triggered Hardware Limit One-Shot Mode 20.6.8. Level Reset, Edge-Triggered Hardware Limit One-Shot Modes 20.6.9. Edge-Triggered Monostable Modes 20.6.10. Level-Triggered Hardware Limit One-Shot Modes 20.7. Timer2 Operation During Sleep 20.8. Register Summary - Timer2 20.9. Register Definitions: Timer2 Control 20.9.1. TxTMR 20.9.2. TxPR 20.9.3. TxCON 20.9.4. TxHLT 20.9.5. TxCLKCON 20.9.6. TxRST 21. Capture/Compare/PWM Module 21.1. CCP Module Configuration 21.1.1. CCP Modules and Timer Resources 21.1.2. Open-Drain Output Option 21.2. Capture Mode 21.2.1. Capture Sources 21.2.2. Timer1 Mode Resource 21.2.3. Software Interrupt Mode 21.2.4. CCP Prescaler 21.2.5. Capture During Sleep 21.3. Compare Mode 21.3.1. CCPx Pin Configuration 21.3.2. Timer1 Mode Resource 21.3.3. Auto-Conversion Trigger 21.3.4. Compare During Sleep 21.4. PWM Overview 21.4.1. Standard PWM Operation 21.4.2. Setup for PWM Operation 21.4.3. Timer2 Timer Resource 21.4.4. PWM Period 21.4.5. PWM Duty Cycle 21.4.6. PWM Resolution 21.4.7. Operation in Sleep Mode 21.4.8. Changes in System Clock Frequency 21.4.9. Effects of Reset 21.5. Register Summary - CCP Control 21.6. Register Definitions: CCP Control 21.6.1. CCPxCON 21.6.2. CCPxCAP 21.6.3. CCPRx 22. (PWM) Pulse-Width Modulation 22.1. Fundamental Operation 22.2. PWM Output Polarity 22.3. PWM Period 22.4. PWM Duty Cycle 22.5. PWM Resolution 22.6. Operation in Sleep Mode 22.7. Changes in System Clock Frequency 22.8. Effects of Reset 22.9. Setup for PWM Operation using PWMx Output Pins 22.9.1. PWMx Pin Configuration 22.10. Setup for PWM Operation to Other Device Peripherals 22.11. Register Summary - Registers Associated with PWM 22.12. Register Definitions: PWM Control 22.12.1. PWMxCON 22.12.2. PWMxDC 23. (ZCD) Zero-Cross Detection Module 23.1. External Resistor Selection 23.2. ZCD Logic Output 23.3. ZCD Logic Polarity 23.4. ZCD Interrupts 23.5. Correction for ZCPINV Offset 23.5.1. Correction by AC Coupling 23.5.2. Correction By Offset Current 23.6. Handling VPEAK Variations 23.7. Operation During Sleep 23.8. Effects of a Reset 23.9. Disabling the ZCD Module 23.10. Register Summary: ZCD Control 23.11. Register Definitions: ZCD Control 23.11.1. ZCDCON 24. (CWG) Complementary Waveform Generator Module 24.1. Fundamental Operation 24.2. Operating Modes 24.2.1. Half-Bridge Mode 24.2.2. Push-Pull Mode 24.2.3. Full-Bridge Modes 24.2.3.1. Direction Change in Full-Bridge Mode 24.2.3.2. Dead-Band Delay in Full-Bridge Mode 24.2.4. Steering Modes 24.2.4.1. Synchronous Steering Mode 24.2.4.2. Asynchronous Steering Mode 24.3. Start-up Considerations 24.4. Clock Source 24.5. Selectable Input Sources 24.6. Output Control 24.6.1. CWG Outputs 24.6.2. Polarity Control 24.7. Dead-Band Control 24.7.1. Dead-Band Functionality in Half-Bridge mode 24.7.2. Dead-Band Functionality in Full-Bridge mode 24.8. Rising Edge and Reverse Dead Band 24.9. Falling Edge and Forward Dead Band 24.10. Dead-Band Jitter 24.11. Auto-Shutdown 24.11.1. Shutdown 24.11.1.1. Software Generated Shutdown 24.11.1.2. External Input Source 24.11.1.3. Pin Override Levels 24.11.1.4. Auto-Shutdown Interrupts 24.11.2. Auto-Shutdown Restart 24.11.2.1. Software-Controlled Restart 24.11.2.2. Auto-Restart 24.12. Operation During Sleep 24.13. Configuring the CWG 24.14. Register Summary - CWG Control 24.15. Register Definitions: CWG Control 24.15.1. CWGxCON0 24.15.2. CWGxCON1 24.15.3. CWGxCLK 24.15.4. CWGxISM 24.15.5. CWGxSTR 24.15.6. CWGxAS0 24.15.7. CWGxAS1 24.15.8. CWGxDBR 24.15.9. CWGxDBF 25. (DSM) Data Signal Modulator Module 25.1. DSM Operation 25.2. Modulator Signal Sources 25.3. Carrier Signal Sources 25.4. Carrier Synchronization 25.5. Carrier Source Polarity Select 25.6. Programmable Modulator Data 25.7. Modulated Output Polarity 25.8. Operation in Sleep Mode 25.9. Effects of a Reset 25.10. Peripheral Module Disable 25.11. Register Summary - DSM 25.12. Register Definitions: Modulation Control 25.12.1. MDCON0 25.12.2. MDCON1 25.12.3. MDCARH 25.12.4. MDCARL 25.12.5. MDSRC 26. (MSSP) Master Synchronous Serial Port Module 26.1. SPI Mode Overview 26.1.1. SPI Mode Registers 26.2. SPI Mode Operation 26.2.1. SPI Master Mode 26.2.2. SPI Slave Mode 26.2.3. Daisy-Chain Configuration 26.2.4. Slave Select Synchronization 26.2.5. SPI Operation in Sleep Mode 26.3. I2C Mode Overview 26.3.1. Register Definitions: I2C Mode 26.4. I2C Mode Operation 26.4.1. Clock Stretching 26.4.2. Arbitration 26.4.3. Byte Format 26.4.4. Definition of I2C Terminology 26.4.5. SDA and SCL Pins 26.4.6. SDA Hold Time 26.4.7. Start Condition 26.4.8. Stop Condition 26.4.9. Restart Condition 26.4.10. Start/Stop Condition Interrupt Masking 26.4.11. Acknowledge Sequence 26.5. I2C Slave Mode Operation 26.5.1. Slave Mode Addresses 26.5.1.1. I2C Slave 7-bit Addressing Mode 26.5.1.2. I2C Slave 10-bit Addressing Mode 26.5.2. Slave Reception 26.5.2.1. 7-bit Addressing Reception 26.5.2.2. 7-bit Reception with AHEN and DHEN 26.5.3. Slave Transmission 26.5.3.1. Slave Mode Bus Collision 26.5.3.2. 7-bit Transmission 26.5.3.3. 7-bit Transmission with Address Hold Enabled 26.5.4. Slave Mode 10-bit Address Reception 26.5.5. 10-bit Addressing with Address or Data Hold 26.5.6. Clock Stretching 26.5.6.1. Normal Clock Stretching 26.5.6.2. 10-bit Addressing Mode 26.5.6.3. Byte NACKing 26.5.7. Clock Synchronization and the CKP bit 26.5.8. General Call Address Support 26.5.9. SSP Mask Register 26.6. I2C Master Mode 26.6.1. I2C Master Mode Operation 26.6.2. Clock Arbitration 26.6.3. WCOL Status Flag 26.6.4. I2C Master Mode Start Condition Timing 26.6.5. I2C Master Mode Repeated Start Condition Timing 26.6.6. I2C Master Mode Transmission 26.6.6.1. BF Status Flag 26.6.6.2. WCOL Status Flag 26.6.6.3. ACKSTAT Status Flag 26.6.6.4. Typical transmit sequence: 26.6.7. I2C Master Mode Reception 26.6.7.1. BF Status Flag 26.6.7.2. SSPOV Status Flag 26.6.7.3. WCOL Status Flag 26.6.7.4. Typical Receive Sequence: 26.6.8. Acknowledge Sequence Timing 26.6.8.1. Acknowledge Write Collision 26.6.9. Stop Condition Timing 26.6.9.1. Write Collision on Stop 26.6.10. Sleep Operation 26.6.11. Effects of a Reset 26.6.12. Multi-Master Mode 26.6.13. Multi -Master Communication, Bus Collision and Bus Arbitration 26.6.13.1. Bus Collision During a Start Condition 26.6.13.2. Bus Collision During a Repeated Start Condition 26.6.13.3. Bus Collision During a Stop Condition 26.7. Baud Rate Generator 26.8. Register Summary: MSSP Control 26.9. Register Definitions: MSSP Control 26.9.1. SSPxSTAT 26.9.2. SSPxCON1 26.9.3. SSPxCON2 26.9.4. SSPxCON3 26.9.5. SSPxBUF 26.9.6. SSPxADD 26.9.7. SSPxMSK 27. (EUSART) Enhanced Universal Synchronous Asynchronous Receiver Transmitter 27.1. EUSART Asynchronous Mode 27.1.1. EUSART Asynchronous Transmitter 27.1.1.1. Enabling the Transmitter 27.1.1.2. Transmitting Data 27.1.1.3. Transmit Data Polarity 27.1.1.4. Transmit Interrupt Flag 27.1.1.5. TSR Status 27.1.1.6. Transmitting 9-Bit Characters 27.1.1.7. Asynchronous Transmission Setup 27.1.2. EUSART Asynchronous Receiver 27.1.2.1. Enabling the Receiver 27.1.2.2. Receiving Data 27.1.2.3. Receive Interrupts 27.1.2.4. Receive Framing Error 27.1.2.5. Receive Overrun Error 27.1.2.6. Receiving 9-Bit Characters 27.1.2.7. Address Detection 27.1.2.8. Asynchronous Reception Setup 27.1.2.9. 9-Bit Address Detection Mode Setup 27.1.3. Clock Accuracy with Asynchronous Operation 27.2. EUSART Baud Rate Generator (BRG) 27.2.1. Auto-Baud Detect 27.2.2. Auto-Baud Overflow 27.2.3. Auto-Wake-up on Break 27.2.3.1. Special Considerations 27.2.4. Break Character Sequence 27.2.4.1. Break and Sync Transmit Sequence 27.2.5. Receiving a Break Character 27.3. EUSART Synchronous Mode 27.3.1. Synchronous Master Mode 27.3.1.1. Master Clock 27.3.1.2. Clock Polarity 27.3.1.3. Synchronous Master Transmission 27.3.1.4. Synchronous Master Transmission Setup 27.3.1.5. Synchronous Master Reception 27.3.1.6. Receive Overrun Error 27.3.1.7. Receiving 9-Bit Characters 27.3.1.8. Synchronous Master Reception Setup 27.3.2. Synchronous Slave Mode 27.3.2.1. Slave Clock 27.3.2.2. EUSART Synchronous Slave Transmit 27.3.2.3. Synchronous Slave Transmission Setup 27.3.2.4. EUSART Synchronous Slave Reception 27.3.2.5. Synchronous Slave Reception Setup: 27.4. EUSART Operation During Sleep 27.4.1. Synchronous Receive During Sleep 27.4.2. Synchronous Transmit During Sleep 27.5. Register Summary - EUSART 27.6. Register Definitions: EUSART Control 27.6.1. RCxSTA 27.6.2. TXxSTA 27.6.3. BAUDxCON 27.6.4. SPxBRG 27.6.5. RCxREG 27.6.6. TXxREG 28. (FVR) Fixed Voltage Reference 28.1. Independent Gain Amplifiers 28.2. FVR Stabilization Period 28.3. Register Summary - FVR 28.4. Register Definitions: FVR Control 28.4.1. FVRCON 29. Temperature Indicator Module 29.1. Circuit Operation 29.2. Minimum Operating VDD 29.3. Temperature Output 29.4. ADC Acquisition Time 30. (DAC) 5-Bit Digital-to-Analog Converter Module 30.1. Output Voltage Selection 30.2. Ratiometric Output Level 30.3. DAC Voltage Reference Output 30.4. Operation During Sleep 30.5. Effects of a Reset 30.6. Register Summary - DAC Control 30.7. Register Definitions: DAC Control 30.7.1. DAC1CON0 30.7.2. DAC1CON1 31. (ADC2) Analog-to-Digital Converter with Computation Module 31.1. ADC Configuration 31.1.1. Port Configuration 31.1.2. Channel Selection 31.1.3. ADC Voltage Reference 31.1.4. Conversion Clock 31.1.5. Interrupts 31.1.6. Result Formatting 31.2. ADC Operation 31.2.1. Starting a Conversion 31.2.2. Completion of a Conversion 31.2.3. Terminating a Conversion 31.2.4. ADC Operation During Sleep 31.2.5. External Trigger During Sleep 31.2.6. Auto-Conversion Trigger 31.2.7. ADC Conversion Procedure (Basic Mode) 31.3. ADC Acquisition Requirements 31.4. Capacitive Voltage Divider (CVD) Features 31.4.1. CVD Operation 31.4.2. PreCharge Control 31.4.3. Acquisition Control for CVD (ADPRE > 0) 31.4.4. Guard Ring Outputs 31.4.5. Additional Sample and Hold Capacitance 31.5. Computation Operation 31.5.1. Digital Filter/Average 31.5.2. Basic Mode 31.5.3. Accumulate Mode 31.5.4. Average Mode 31.5.5. Burst Average Mode 31.5.6. Low-pass Filter Mode 31.5.7. Threshold Comparison 31.5.8. Continuous Sampling Mode 31.5.9. Double Sample Conversion 31.6. Register Summary - ADC Control 31.7. Register Definitions: ADC Control 31.7.1. ADCON0 31.7.2. ADCON1 31.7.3. ADCON2 31.7.4. ADCON3 31.7.5. ADSTAT 31.7.6. ADCLK 31.7.7. ADREF 31.7.8. ADPCH 31.7.9. ADPRE 31.7.10. ADACQ 31.7.11. ADCAP 31.7.12. ADRPT 31.7.13. ADCNT 31.7.14. ADFLTR 31.7.15. ADRES 31.7.16. ADPREV 31.7.17. ADACC 31.7.18. ADSTPT 31.7.19. ADERR 31.7.20. ADLTH 31.7.21. ADUTH 31.7.22. ADACT 32. (CMP) Comparator Module 32.1. Comparator Overview 32.2. Comparator Control 32.2.1. Comparator Enable 32.2.2. Comparator Output 32.2.3. Comparator Output Polarity 32.3. Comparator Hysteresis 32.4. Operation With Timer1 Gate 32.4.1. Comparator Output Synchronization 32.5. Comparator Interrupt 32.6. Comparator Positive Input Selection 32.7. Comparator Negative Input Selection 32.8. Comparator Response Time 32.9. Analog Input Connection Considerations 32.10. CWG1 Auto-Shutdown Source 32.11. ADC Auto-Trigger Source 32.12. Even Numbered Timers Reset 32.13. Operation in Sleep Mode 32.14. Register Summary - Comparator 32.15. Register Definitions: Comparator Control 32.15.1. CMxCON0 32.15.2. CMxCON1 32.15.3. CMxNCH 32.15.4. CMxPCH 32.15.5. CMOUT 33. (HLVD) High/Low-Voltage Detect 33.1. Operation 33.2. Setup 33.3. Current Consumption 33.4. HLVD Start-up Time 33.5. Applications 33.6. Operation During Sleep 33.7. Operation During Idle and Doze Modes 33.8. Effects of a Reset 33.9. Register Summary - HLVD 33.10. Register Definitions: HLVD Control 33.10.1. HLVDCON0 33.10.2. HLVDCON1 34. In-Circuit Serial Programming™ (ICSP™) 34.1. High-Voltage Programming Entry Mode 34.2. Low-Voltage Programming Entry Mode 34.3. Common Programming Interfaces 35. Register Summary 36. Instruction Set Summary 36.1. Standard Instruction Set 36.1.1. Standard Instruction Set
 36.2. Extended Instruction Set 36.2.1. Extended Instruction Syntax 36.2.2. Extended Instruction Set 36.2.3. Byte-Oriented and 
Bit-Oriented Instructions in Indexed Literal Offset Mode 36.2.3.1. Extended Instruction Syntax with Standard PIC18 Commands 36.2.4. Considerations when Enabling the Extended Instruction Set 36.2.5. Special Considerations with Microchip MPLAB® IDE Tools 37. Development Support 37.1. MPLAB X Integrated Development Environment Software 37.2. MPLAB XC Compilers 37.3. MPASM Assembler 37.4. MPLINK Object Linker/MPLIB Object Librarian 37.5. MPLAB Assembler, Linker and Librarian for Various Device Families 37.6. MPLAB X SIM Software Simulator 37.7. MPLAB REAL ICE In-Circuit Emulator System 37.8. MPLAB ICD 3 In-Circuit Debugger System 37.9. PICkit 3 In-Circuit Debugger/Programmer 37.10. MPLAB PM3 Device Programmer 37.11. Demonstration/Development Boards, Evaluation Kits, and Starter Kits 37.12. Third-Party Development Tools 38. Electrical Specifications 38.1. Absolute Maximum Ratings(†) 38.2. Standard Operating Conditions 38.3. DC Characteristics 38.3.1. Supply Voltage 38.3.2. Supply Current (IDD)(1,2,4) 38.3.3. Power-Down Current (IPD)(1,2) 38.3.4. I/O Ports 38.3.5. Memory Programming Specifications 38.3.6. Thermal Characteristics 38.4. AC Characteristics 38.4.1. External Clock/Oscillator Timing Requirements 38.4.2. Internal Oscillator Parameters(1) 38.4.3. PLL Specifications 38.4.4. I/O and CLKOUT Timing Specifications 38.4.5. Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications 38.4.6. High/Low-Voltage Detect Characteristics 38.4.7. Analog-To-Digital Converter (ADC) Accuracy Specifications(1,2) 38.4.8. Analog-to-Digital Converter (ADC) Conversion Timing Specifications 38.4.9. Comparator Specifications 38.4.10. 5-Bit DAC Specifications 38.4.11. Fixed Voltage Reference (FVR) Specifications 38.4.12. Zero Cross Detect (ZCD) Specifications 38.4.13. Timer0 and Timer1 External Clock Requirements 38.4.14. Capture/Compare/PWM Requirements (CCP) 38.4.15. EUSART Synchronous Transmission Requirements 38.4.16. EUSART Synchronous Receive Requirements 38.4.17. SPI Mode Requirements 38.4.18. I2C Bus Start/Stop Bits Requirements 38.4.19. I2C Bus Data Requirements 39. DC and AC Characteristics Graphs and Tables 39.1. Graphs 40. Packaging Information 40.1. Package Details 41. Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service